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[RISCV] Add Smrnmi extension (#111668)
This commit has completed the Extension for Resumable Non Maskable Interrupts, adding four CRSs and one Trap-Return instruction. Specification link:["Smrnmi" Extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/rnmi.adoc) --------- Co-authored-by: Sam Elliott <[email protected]>
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -120,6 +120,7 @@
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// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
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// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
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// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
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// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts)
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// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
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// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
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// CHECK-NEXT: ssccfg 1.0 'Ssccfg' (Counter Configuration Supervisor Level)

‎clang/test/Preprocessor/riscv-target-features.c

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// CHECK-NOT: __riscv_smcdeleg {{.*$}}
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// CHECK-NOT: __riscv_smcsrind {{.*$}}
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// CHECK-NOT: __riscv_smepmp {{.*$}}
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// CHECK-NOT: __riscv_smrnmi {{.*$}}
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// CHECK-NOT: __riscv_smstateen {{.*$}}
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// CHECK-NOT: __riscv_ssaia {{.*$}}
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// CHECK-NOT: __riscv_ssccfg {{.*$}}
@@ -1449,6 +1450,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s
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// CHECK-SMEPMP-EXT: __riscv_smepmp 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismrnmi1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64ismrnmi1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMRNMI-EXT %s
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// CHECK-SMRNMI-EXT: __riscv_smrnmi 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32izfa -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -129,6 +129,7 @@ on support follow.
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``Smcdeleg`` Supported
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``Smcsrind`` Supported
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``Smepmp`` Supported
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``Smrnmi`` Assembly Support
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``Smstateen`` Assembly Support
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``Ssaia`` Supported
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``Ssccfg`` Supported

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -931,6 +931,13 @@ def FeatureStdExtSmepmp
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: RISCVExtension<"smepmp", 1, 0,
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"'Smepmp' (Enhanced Physical Memory Protection)">;
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def FeatureStdExtSmrnmi
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: RISCVExtension<"smrnmi", 1, 0,
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"'Smrnmi' (Resumable Non-Maskable Interrupts)">;
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def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">,
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AssemblerPredicate<(all_of FeatureStdExtSmrnmi),
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"'Smrnmi' (Resumable Non-Maskable Interrupts)">;
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def FeatureStdExtSmcdeleg
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: RISCVExtension<"smcdeleg", 1, 0,
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"'Smcdeleg' (Counter Delegation Machine Level)">;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -815,6 +815,14 @@ def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
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}
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} // isBarrier = 1, isReturn = 1, isTerminator = 1
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let Predicates = [HasStdExtSmrnmi] in {
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def MNRET : Priv<"mnret", 0b0111000>, Sched<[]> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00010;
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}
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}// Predicates = [HasStdExtSmrnmi]
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def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
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let rd = 0;
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let rs1 = 0;

‎llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
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; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s
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; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s
@@ -261,6 +262,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
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; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s
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; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s
@@ -410,6 +412,7 @@
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; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
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; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
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; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
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; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0"
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; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
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; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
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; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
@@ -551,6 +554,7 @@
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; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
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; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
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; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
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; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0"
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; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
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; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
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; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32i_smepmp1p0"
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# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
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.attribute arch, "rv32i_smrnmi1p0"
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# CHECK: attribute 5, "rv32i2p1_smrnmi1p0"
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.attribute arch, "rv32i_ssccfg1p0"
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# CHECK: attribute 5, "rv32i2p1_ssccfg1p0"
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‎llvm/test/MC/RISCV/machine-csr-names.s

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@@ -1913,6 +1913,66 @@ csrrs t1, mhpmcounter31, zero
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csrrs t2, 0xB1F, zero
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######################################
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# Machine Counter Setup
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######################################
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# mnscratch
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# name
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# CHECK-INST: csrrs t1, mnscratch, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x74]
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# CHECK-INST-ALIAS: csrr t1, mnscratch
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# uimm12
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# CHECK-INST: csrrs t2, mnscratch, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x74]
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# CHECK-INST-ALIAS: csrr t2, mnscratch
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# name
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csrrs t1, mnscratch, zero
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# uimm12
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csrrs t2, 0x740, zero
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# mnepc
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# name
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# CHECK-INST: csrrs t1, mnepc, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x74]
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# CHECK-INST-ALIAS: csrr t1, mnepc
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# uimm12
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# CHECK-INST: csrrs t2, mnepc, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x74]
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# CHECK-INST-ALIAS: csrr t2, mnepc
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# name
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csrrs t1, mnepc, zero
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# uimm12
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csrrs t2, 0x741, zero
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# mncause
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# name
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# CHECK-INST: csrrs t1, mncause, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0x74]
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# CHECK-INST-ALIAS: csrr t1, mncause
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# uimm12
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# CHECK-INST: csrrs t2, mncause, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x74]
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# CHECK-INST-ALIAS: csrr t2, mncause
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# name
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csrrs t1, mncause, zero
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# uimm12
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csrrs t2, 0x742, zero
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# mnstatus
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# name
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# CHECK-INST: csrrs t1, mnstatus, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x40,0x74]
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# CHECK-INST-ALIAS: csrr t1, mnstatus
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# uimm12
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# CHECK-INST: csrrs t2, mnstatus, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x74]
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# CHECK-INST-ALIAS: csrr t2, mnstatus
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# name
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csrrs t1, mnstatus, zero
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# uimm12
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csrrs t2, 0x744, zero
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######################################
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# Machine Counter Setup
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######################################

‎llvm/test/MC/RISCV/smrnmi-invalid.s

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# RUN: not llvm-mc -triple riscv32 -mattr=+smrnmi < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+smrnmi < %s 2>&1 | FileCheck %s
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mnret 0x10 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction

‎llvm/test/MC/RISCV/smrnmi-valid.s

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+smrnmi -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+smrnmi -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smrnmi < %s \
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# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smrnmi < %s \
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# RUN: | llvm-objdump --mattr=+smrnmi -M no-aliases -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: mnret
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# CHECK: encoding: [0x73,0x00,0x20,0x70]
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mnret

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1065,6 +1065,7 @@ R"(All available -march extensions for RISC-V
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smcdeleg 1.0
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smcsrind 1.0
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smepmp 1.0
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smrnmi 1.0
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smstateen 1.0
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ssaia 1.0
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ssccfg 1.0

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