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[RISCV] Fix vfwcvt/vfncvt pseudos w/ rounding mode lowering
Some signed opcodes were being lowered to their unsigned counterparts and vice-versa. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154234
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4 files changed

+39
-39
lines changed

4 files changed

+39
-39
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -14096,15 +14096,15 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1409614096
// =========================================================================
1409714097

1409814098
case RISCV::PseudoVFWCVT_RM_XU_F_V_M1_MASK:
14099-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK);
14099+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M1_MASK);
1410014100
case RISCV::PseudoVFWCVT_RM_XU_F_V_M2_MASK:
14101-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M2_MASK);
14101+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M2_MASK);
1410214102
case RISCV::PseudoVFWCVT_RM_XU_F_V_M4_MASK:
14103-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M4_MASK);
14103+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_M4_MASK);
1410414104
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF2_MASK:
14105-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF2_MASK);
14105+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF2_MASK);
1410614106
case RISCV::PseudoVFWCVT_RM_XU_F_V_MF4_MASK:
14107-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_MF4_MASK);
14107+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_XU_F_V_MF4_MASK);
1410814108

1410914109
case RISCV::PseudoVFWCVT_RM_X_F_V_M1_MASK:
1411014110
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_X_F_V_M1_MASK);
@@ -14131,32 +14131,32 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1413114131
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK);
1413214132

1413314133
case RISCV::PseudoVFWCVT_RM_F_X_V_M1_MASK:
14134-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M1_MASK);
14134+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M1_MASK);
1413514135
case RISCV::PseudoVFWCVT_RM_F_X_V_M2_MASK:
14136-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M2_MASK);
14136+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M2_MASK);
1413714137
case RISCV::PseudoVFWCVT_RM_F_X_V_M4_MASK:
14138-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_M4_MASK);
14138+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_M4_MASK);
1413914139
case RISCV::PseudoVFWCVT_RM_F_X_V_MF2_MASK:
14140-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF2_MASK);
14140+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF2_MASK);
1414114141
case RISCV::PseudoVFWCVT_RM_F_X_V_MF4_MASK:
14142-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF4_MASK);
14142+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF4_MASK);
1414314143
case RISCV::PseudoVFWCVT_RM_F_X_V_MF8_MASK:
14144-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_XU_V_MF8_MASK);
14144+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFWCVT_F_X_V_MF8_MASK);
1414514145

1414614146
// =========================================================================
1414714147
// VFNCVT
1414814148
// =========================================================================
1414914149

1415014150
case RISCV::PseudoVFNCVT_RM_XU_F_W_M1_MASK:
14151-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M1_MASK);
14151+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M1_MASK);
1415214152
case RISCV::PseudoVFNCVT_RM_XU_F_W_M2_MASK:
14153-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M2_MASK);
14153+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M2_MASK);
1415414154
case RISCV::PseudoVFNCVT_RM_XU_F_W_M4_MASK:
14155-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_M4_MASK);
14155+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_M4_MASK);
1415614156
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF2_MASK:
14157-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF2_MASK);
14157+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF2_MASK);
1415814158
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF4_MASK:
14159-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_X_F_W_MF4_MASK);
14159+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF4_MASK);
1416014160
case RISCV::PseudoVFNCVT_RM_XU_F_W_MF8_MASK:
1416114161
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_XU_F_W_MF8_MASK);
1416214162

@@ -14185,15 +14185,15 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1418514185
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK);
1418614186

1418714187
case RISCV::PseudoVFNCVT_RM_F_X_W_M1_MASK:
14188-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M1_MASK);
14188+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M1_MASK);
1418914189
case RISCV::PseudoVFNCVT_RM_F_X_W_M2_MASK:
14190-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M2_MASK);
14190+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M2_MASK);
1419114191
case RISCV::PseudoVFNCVT_RM_F_X_W_M4_MASK:
14192-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_M4_MASK);
14192+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_M4_MASK);
1419314193
case RISCV::PseudoVFNCVT_RM_F_X_W_MF2_MASK:
14194-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF2_MASK);
14194+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF2_MASK);
1419514195
case RISCV::PseudoVFNCVT_RM_F_X_W_MF4_MASK:
14196-
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_XU_W_MF4_MASK);
14196+
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFNCVT_F_X_W_MF4_MASK);
1419714197

1419814198
case RISCV::PseudoVFROUND_NOEXCEPT_V_M1_MASK:
1419914199
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK,

‎llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -705,7 +705,7 @@ define <vscale x 1 x i32> @ceil_nxv1f64_to_ui32(<vscale x 1 x double> %x) {
705705
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
706706
; RV32-NEXT: vmset.m v0
707707
; RV32-NEXT: fsrmi a0, 3
708-
; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
708+
; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
709709
; RV32-NEXT: fsrm a0
710710
; RV32-NEXT: vmv1r.v v8, v9
711711
; RV32-NEXT: ret
@@ -715,7 +715,7 @@ define <vscale x 1 x i32> @ceil_nxv1f64_to_ui32(<vscale x 1 x double> %x) {
715715
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
716716
; RV64-NEXT: vmset.m v0
717717
; RV64-NEXT: fsrmi a0, 3
718-
; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
718+
; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
719719
; RV64-NEXT: fsrm a0
720720
; RV64-NEXT: vmv1r.v v8, v9
721721
; RV64-NEXT: ret
@@ -987,7 +987,7 @@ define <vscale x 4 x i32> @ceil_nxv4f64_to_ui32(<vscale x 4 x double> %x) {
987987
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
988988
; RV32-NEXT: vmset.m v0
989989
; RV32-NEXT: fsrmi a0, 3
990-
; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t
990+
; RV32-NEXT: vfncvt.xu.f.w v12, v8, v0.t
991991
; RV32-NEXT: fsrm a0
992992
; RV32-NEXT: vmv.v.v v8, v12
993993
; RV32-NEXT: ret
@@ -997,7 +997,7 @@ define <vscale x 4 x i32> @ceil_nxv4f64_to_ui32(<vscale x 4 x double> %x) {
997997
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
998998
; RV64-NEXT: vmset.m v0
999999
; RV64-NEXT: fsrmi a0, 3
1000-
; RV64-NEXT: vfncvt.x.f.w v12, v8, v0.t
1000+
; RV64-NEXT: vfncvt.xu.f.w v12, v8, v0.t
10011001
; RV64-NEXT: fsrm a0
10021002
; RV64-NEXT: vmv.v.v v8, v12
10031003
; RV64-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -515,7 +515,7 @@ define <vscale x 1 x i16> @ceil_nxv1f32_to_ui16(<vscale x 1 x float> %x) {
515515
; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
516516
; RV32-NEXT: vmset.m v0
517517
; RV32-NEXT: fsrmi a0, 3
518-
; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
518+
; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
519519
; RV32-NEXT: fsrm a0
520520
; RV32-NEXT: vmv1r.v v8, v9
521521
; RV32-NEXT: ret
@@ -525,7 +525,7 @@ define <vscale x 1 x i16> @ceil_nxv1f32_to_ui16(<vscale x 1 x float> %x) {
525525
; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
526526
; RV64-NEXT: vmset.m v0
527527
; RV64-NEXT: fsrmi a0, 3
528-
; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
528+
; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
529529
; RV64-NEXT: fsrm a0
530530
; RV64-NEXT: vmv1r.v v8, v9
531531
; RV64-NEXT: ret
@@ -611,7 +611,7 @@ define <vscale x 1 x i64> @ceil_nxv1f32_to_ui64(<vscale x 1 x float> %x) {
611611
; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
612612
; RV32-NEXT: vmset.m v0
613613
; RV32-NEXT: fsrmi a0, 3
614-
; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
614+
; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
615615
; RV32-NEXT: fsrm a0
616616
; RV32-NEXT: vmv1r.v v8, v9
617617
; RV32-NEXT: ret
@@ -621,7 +621,7 @@ define <vscale x 1 x i64> @ceil_nxv1f32_to_ui64(<vscale x 1 x float> %x) {
621621
; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
622622
; RV64-NEXT: vmset.m v0
623623
; RV64-NEXT: fsrmi a0, 3
624-
; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
624+
; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
625625
; RV64-NEXT: fsrm a0
626626
; RV64-NEXT: vmv1r.v v8, v9
627627
; RV64-NEXT: ret
@@ -753,7 +753,7 @@ define <vscale x 4 x i16> @ceil_nxv4f32_to_ui16(<vscale x 4 x float> %x) {
753753
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
754754
; RV32-NEXT: vmset.m v0
755755
; RV32-NEXT: fsrmi a0, 3
756-
; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t
756+
; RV32-NEXT: vfncvt.xu.f.w v10, v8, v0.t
757757
; RV32-NEXT: fsrm a0
758758
; RV32-NEXT: vmv.v.v v8, v10
759759
; RV32-NEXT: ret
@@ -763,7 +763,7 @@ define <vscale x 4 x i16> @ceil_nxv4f32_to_ui16(<vscale x 4 x float> %x) {
763763
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
764764
; RV64-NEXT: vmset.m v0
765765
; RV64-NEXT: fsrmi a0, 3
766-
; RV64-NEXT: vfncvt.x.f.w v10, v8, v0.t
766+
; RV64-NEXT: vfncvt.xu.f.w v10, v8, v0.t
767767
; RV64-NEXT: fsrm a0
768768
; RV64-NEXT: vmv.v.v v8, v10
769769
; RV64-NEXT: ret
@@ -849,7 +849,7 @@ define <vscale x 4 x i64> @ceil_nxv4f32_to_ui64(<vscale x 4 x float> %x) {
849849
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
850850
; RV32-NEXT: vmset.m v0
851851
; RV32-NEXT: fsrmi a0, 3
852-
; RV32-NEXT: vfwcvt.x.f.v v12, v8, v0.t
852+
; RV32-NEXT: vfwcvt.xu.f.v v12, v8, v0.t
853853
; RV32-NEXT: fsrm a0
854854
; RV32-NEXT: vmv4r.v v8, v12
855855
; RV32-NEXT: ret
@@ -859,7 +859,7 @@ define <vscale x 4 x i64> @ceil_nxv4f32_to_ui64(<vscale x 4 x float> %x) {
859859
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
860860
; RV64-NEXT: vmset.m v0
861861
; RV64-NEXT: fsrmi a0, 3
862-
; RV64-NEXT: vfwcvt.x.f.v v12, v8, v0.t
862+
; RV64-NEXT: vfwcvt.xu.f.v v12, v8, v0.t
863863
; RV64-NEXT: fsrm a0
864864
; RV64-NEXT: vmv4r.v v8, v12
865865
; RV64-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -517,7 +517,7 @@ define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
517517
; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
518518
; RV32-NEXT: vmset.m v0
519519
; RV32-NEXT: fsrmi a0, 3
520-
; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
520+
; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
521521
; RV32-NEXT: fsrm a0
522522
; RV32-NEXT: vmv1r.v v8, v9
523523
; RV32-NEXT: ret
@@ -527,7 +527,7 @@ define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
527527
; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
528528
; RV64-NEXT: vmset.m v0
529529
; RV64-NEXT: fsrmi a0, 3
530-
; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
530+
; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
531531
; RV64-NEXT: fsrm a0
532532
; RV64-NEXT: vmv1r.v v8, v9
533533
; RV64-NEXT: ret
@@ -655,7 +655,7 @@ define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
655655
; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
656656
; RV32-NEXT: vmset.m v0
657657
; RV32-NEXT: fsrmi a0, 3
658-
; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
658+
; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
659659
; RV32-NEXT: fsrm a0
660660
; RV32-NEXT: vmv1r.v v8, v9
661661
; RV32-NEXT: ret
@@ -665,7 +665,7 @@ define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
665665
; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
666666
; RV64-NEXT: vmset.m v0
667667
; RV64-NEXT: fsrmi a0, 3
668-
; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
668+
; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
669669
; RV64-NEXT: fsrm a0
670670
; RV64-NEXT: vmv1r.v v8, v9
671671
; RV64-NEXT: ret
@@ -751,7 +751,7 @@ define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
751751
; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
752752
; RV32-NEXT: vmset.m v0
753753
; RV32-NEXT: fsrmi a0, 3
754-
; RV32-NEXT: vfwcvt.x.f.v v10, v8, v0.t
754+
; RV32-NEXT: vfwcvt.xu.f.v v10, v8, v0.t
755755
; RV32-NEXT: fsrm a0
756756
; RV32-NEXT: vmv2r.v v8, v10
757757
; RV32-NEXT: ret
@@ -761,7 +761,7 @@ define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
761761
; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
762762
; RV64-NEXT: vmset.m v0
763763
; RV64-NEXT: fsrmi a0, 3
764-
; RV64-NEXT: vfwcvt.x.f.v v10, v8, v0.t
764+
; RV64-NEXT: vfwcvt.xu.f.v v10, v8, v0.t
765765
; RV64-NEXT: fsrm a0
766766
; RV64-NEXT: vmv2r.v v8, v10
767767
; RV64-NEXT: ret

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