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AMDGPU: Replace <8 x i32> undef uses in tests with poison
1 parent 4a77200 commit dee83a2

17 files changed

+44
-44
lines changed

‎llvm/test/CodeGen/AMDGPU/adjust-writemask-invalid-copy.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
; GCN: buffer_store_dword v0
88
define amdgpu_ps void @adjust_writemask_crash_0_nochain() #0 {
99
main_body:
10-
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
10+
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
1111
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
1212
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
1313
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -23,7 +23,7 @@ main_body:
2323
; GCN: buffer_store_dword v0
2424
define amdgpu_ps void @adjust_writemask_crash_1_nochain() #0 {
2525
main_body:
26-
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
26+
%tmp = call <2 x float> @llvm.amdgcn.image.getlod.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
2727
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
2828
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
2929
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -39,7 +39,7 @@ main_body:
3939
; GCN: buffer_store_dword v0
4040
define amdgpu_ps void @adjust_writemask_crash_0_chain() #0 {
4141
main_body:
42-
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
42+
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
4343
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
4444
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
4545
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -55,7 +55,7 @@ main_body:
5555
; GCN: buffer_store_dword v0
5656
define amdgpu_ps void @adjust_writemask_crash_1_chain() #0 {
5757
main_body:
58-
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
58+
%tmp = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
5959
%tmp1 = bitcast <2 x float> %tmp to <2 x i32>
6060
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
6161
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>
@@ -66,7 +66,7 @@ main_body:
6666

6767
define amdgpu_ps void @adjust_writemask_crash_0_v4() #0 {
6868
main_body:
69-
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
69+
%tmp = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 5, float undef, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
7070
%tmp1 = bitcast <4 x float> %tmp to <4 x i32>
7171
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> poison, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>
7272
%tmp3 = bitcast <4 x i32> %tmp2 to <4 x float>

‎llvm/test/CodeGen/AMDGPU/commute-shifts.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
3030
; VI-NEXT: ; return to shader part epilog
3131
bb:
3232
%tmp = fptosi float %arg0 to i32
33-
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
33+
%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> poison, i32 0, i32 0)
3434
%tmp2.f = extractelement <4 x float> %tmp1, i32 0
3535
%tmp2 = bitcast float %tmp2.f to i32
3636
%tmp3 = and i32 %tmp, 7

‎llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -143,21 +143,21 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
143143
; GFX11-NEXT: v_max_f32_e32 v0, 0, v1
144144
; GFX11-NEXT: ; return to shader part epilog
145145
.entry:
146-
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
146+
%0 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
147147
%.i2243 = extractelement <3 x float> %0, i32 2
148148
%1 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 0, i32 0)
149149
%2 = shufflevector <3 x i32> %1, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
150150
%3 = bitcast <4 x i32> %2 to <4 x float>
151151
%.i2248 = extractelement <4 x float> %3, i32 2
152152
%.i2249 = fmul reassoc nnan nsz arcp contract afn float %.i2243, %.i2248
153153
%4 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
154-
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
154+
%5 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
155155
%.i2333 = extractelement <3 x float> %5, i32 2
156156
%6 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
157-
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
157+
%7 = call <2 x float> @llvm.amdgcn.image.sample.2d.v2f32.f32(i32 3, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
158158
%.i1408 = extractelement <2 x float> %7, i32 1
159159
%.i0364 = extractelement <2 x float> %7, i32 0
160-
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
160+
%8 = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
161161
%9 = call <3 x i32> @llvm.amdgcn.s.buffer.load.v3i32(<4 x i32> poison, i32 112, i32 0)
162162
%10 = shufflevector <3 x i32> %9, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
163163
%11 = bitcast <4 x i32> %10 to <4 x float>
@@ -204,10 +204,10 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
204204
%40 = fmul reassoc nnan nsz arcp contract afn float %39, 0x3F847AE140000000
205205
%41 = fadd reassoc nnan nsz arcp contract afn float %40, 0x3F947AE140000000
206206
%.i2415 = fmul reassoc nnan nsz arcp contract afn float %.i2407, %41
207-
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> undef, i32 0, i32 0)
207+
%42 = call <3 x float> @llvm.amdgcn.image.load.mip.2d.v3f32.i32(i32 7, i32 undef, i32 undef, i32 0, <8 x i32> poison, i32 0, i32 0)
208208
%.i2521 = extractelement <3 x float> %42, i32 2
209209
%43 = call reassoc nnan nsz arcp contract afn float @llvm.amdgcn.fmed3.f32(float undef, float 0.000000e+00, float 1.000000e+00)
210-
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
210+
%44 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
211211
%.i2465 = extractelement <3 x float> %44, i32 2
212212
%.i2466 = fmul reassoc nnan nsz arcp contract afn float %.i2465, %43
213213
%.i2469 = fmul reassoc nnan nsz arcp contract afn float %.i2415, %.i2466
@@ -224,7 +224,7 @@ define amdgpu_ps float @_amdgpu_ps_main() #0 {
224224
%.i2488 = fmul reassoc nnan nsz arcp contract afn float %.i2249, %18
225225
%.i2491 = fmul reassoc nnan nsz arcp contract afn float %.i2485, %4
226226
%.i2494 = fadd reassoc nnan nsz arcp contract afn float %.i2479, %.i2491
227-
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
227+
%51 = call <3 x float> @llvm.amdgcn.image.sample.2d.v3f32.f32(i32 7, float undef, float undef, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
228228
%.i2515 = extractelement <3 x float> %51, i32 2
229229
%.i2516 = fadd reassoc nnan nsz arcp contract afn float %.i2515, %.i2494
230230
%.i2522 = fadd reassoc nnan nsz arcp contract afn float %.i2521, %.i2516

‎llvm/test/CodeGen/AMDGPU/else.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ if:
4141

4242
else:
4343
%c = fmul float %v, 3.0
44-
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
44+
%tex = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %c, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
4545
%v.else = extractelement <4 x float> %tex, i32 0
4646
br label %end
4747

‎llvm/test/CodeGen/AMDGPU/img-nouse-adjust.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
; GCN: IMAGE_LOAD_V4_V2
1212
define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
1313
.entry:
14-
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
14+
%unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> poison, i32 0, i32 0) #3
1515
call void asm sideeffect ";", "" () #0
1616
ret void
1717
}

‎llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -390,7 +390,7 @@ define <4 x float> @insertelement_to_sgpr() nounwind {
390390
; GCN-NEXT: s_setpc_b64 s[30:31]
391391
%tmp = load <4 x i32>, ptr addrspace(4) undef
392392
%tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0
393-
%tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
393+
%tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> poison, <4 x i32> %tmp1, i1 0, i32 0, i32 0)
394394
ret <4 x float> %tmp2
395395
}
396396

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define amdgpu_ps float @test2() #0 {
2828
%live = call i1 @llvm.amdgcn.ps.live()
2929
%live.32 = zext i1 %live to i32
3030
%live.32.bc = bitcast i32 %live.32 to float
31-
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0)
31+
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %live.32.bc, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0)
3232
%r = extractelement <4 x float> %t, i32 0
3333
ret float %r
3434
}
@@ -51,7 +51,7 @@ dead:
5151
end:
5252
%tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ]
5353
%tc.bc = bitcast i32 %tc to float
54-
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> undef, <4 x i32> poison, i1 0, i32 0, i32 0) #0
54+
%t = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %tc.bc, <8 x i32> poison, <4 x i32> poison, i1 0, i32 0, i32 0) #0
5555
%r = extractelement <4 x float> %t, i32 0
5656
ret float %r
5757
}

‎llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define amdgpu_hs void @_amdgpu_hs_main() #0 {
1313
define amdgpu_ps void @_amdgpu_ps_main(i32 %arg) local_unnamed_addr #1 {
1414
.entry:
1515
%tmp = tail call float @llvm.amdgcn.interp.p2(float undef, float undef, i32 1, i32 0, i32 %arg) #2
16-
%tmp1 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float %tmp, <8 x i32> undef, <4 x i32> poison, i1 false, i32 0, i32 0)
16+
%tmp1 = tail call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float undef, float %tmp, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0)
1717
%tmp2 = fcmp olt float %tmp1, 5.000000e-01
1818
br i1 %tmp2, label %bb, label %l
1919

‎llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ define void @alloca_load_store_ptr_mixed_ptrvec(<2 x ptr addrspace(3)> %arg) {
161161
; CHECK-NEXT: entry:
162162
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr addrspace(3)> [[ARG]] to <2 x i32>
163163
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0
164-
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 0
164+
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> poison, i32 [[TMP1]], i32 0
165165
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1
166166
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[TMP3]], i32 1
167167
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0

‎llvm/test/CodeGen/AMDGPU/sgpr-copy.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,7 @@ bb:
383383
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
384384
%tmp7 = getelementptr [17 x <4 x i32>], ptr addrspace(4) %arg, i32 0, i32 %tid
385385
%tmp8 = load <4 x i32>, ptr addrspace(4) %tmp7, align 16, !tbaa !0
386-
%tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> undef, <4 x i32> %tmp8, i1 0, i32 0, i32 0)
386+
%tmp = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float 7.500000e-01, float 2.500000e-01, <8 x i32> poison, <4 x i32> %tmp8, i1 0, i32 0, i32 0)
387387
%tmp10 = extractelement <4 x float> %tmp, i32 0
388388
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
389389
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0

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