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[x86] combineMul - handle 0/-1 KnownBits cases before MUL_IMM logic (REAPPLIED)
Followup to 3d862c7 fix - always fold multiply to zero/negation
1 parent e0b24d9 commit db13404

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2 files changed

+25
-65
lines changed

2 files changed

+25
-65
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

+18-12
Original file line numberDiff line numberDiff line change
@@ -48476,28 +48476,34 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
4847648476
if (DCI.isBeforeLegalize() && VT.isVector())
4847748477
return reduceVMULWidth(N, DL, DAG, Subtarget);
4847848478

48479-
// Optimize a single multiply with constant into two operations in order to
48480-
// implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
48481-
if (!MulConstantOptimization)
48479+
if (VT != MVT::i64 && VT != MVT::i32 &&
48480+
(!VT.isVector() || !VT.isSimple() || !VT.isInteger()))
4848248481
return SDValue();
4848348482

48484-
// An imul is usually smaller than the alternative sequence.
48485-
if (DAG.getMachineFunction().getFunction().hasMinSize())
48483+
KnownBits Known1 = DAG.computeKnownBits(N->getOperand(1));
48484+
if (!Known1.isConstant())
4848648485
return SDValue();
4848748486

48488-
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
48487+
const APInt &C = Known1.getConstant();
48488+
if (C.isZero())
48489+
return DAG.getConstant(0, DL, VT);
48490+
48491+
if (C.isAllOnes())
48492+
return DAG.getNegative(N->getOperand(0), DL, VT);
48493+
48494+
if (isPowerOf2_64(C.getZExtValue()))
4848948495
return SDValue();
4849048496

48491-
if (VT != MVT::i64 && VT != MVT::i32 &&
48492-
(!VT.isVector() || !VT.isSimple() || !VT.isInteger()))
48497+
// Optimize a single multiply with constant into two operations in order to
48498+
// implement it with two cheaper instructions, e.g. LEA + SHL, LEA + LEA.
48499+
if (!MulConstantOptimization)
4849348500
return SDValue();
4849448501

48495-
KnownBits Known1 = DAG.computeKnownBits(N->getOperand(1));
48496-
if (!Known1.isConstant())
48502+
// An imul is usually smaller than the alternative sequence.
48503+
if (DAG.getMachineFunction().getFunction().hasMinSize())
4849748504
return SDValue();
4849848505

48499-
const APInt &C = Known1.getConstant();
48500-
if (isPowerOf2_64(C.getZExtValue()) || C.isZero() || C.isAllOnes())
48506+
if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4850148507
return SDValue();
4850248508

4850348509
int64_t SignMulAmt = C.getSExtValue();

llvm/test/CodeGen/X86/mul-constant-i64.ll

+7-53
Original file line numberDiff line numberDiff line change
@@ -1642,59 +1642,13 @@ define i64 @PR111325(i64 %a0, i1 %a1) {
16421642
; X86-NOOPT-NEXT: xorl %edx, %edx
16431643
; X86-NOOPT-NEXT: retl
16441644
;
1645-
; X64-HSW-LABEL: PR111325:
1646-
; X64-HSW: # %bb.0: # %entry
1647-
; X64-HSW-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1648-
; X64-HSW-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1649-
; X64-HSW-NEXT: imull %edi, %eax
1650-
; X64-HSW-NEXT: testb $1, %sil
1651-
; X64-HSW-NEXT: cmoveq %rcx, %rax
1652-
; X64-HSW-NEXT: retq
1653-
;
1654-
; X64-JAG-LABEL: PR111325:
1655-
; X64-JAG: # %bb.0: # %entry
1656-
; X64-JAG-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1657-
; X64-JAG-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1658-
; X64-JAG-NEXT: imull %edi, %eax
1659-
; X64-JAG-NEXT: testb $1, %sil
1660-
; X64-JAG-NEXT: cmoveq %rcx, %rax
1661-
; X64-JAG-NEXT: retq
1662-
;
1663-
; X64-SLM-LABEL: PR111325:
1664-
; X64-SLM: # %bb.0: # %entry
1665-
; X64-SLM-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1666-
; X64-SLM-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1667-
; X64-SLM-NEXT: imull %edi, %eax
1668-
; X64-SLM-NEXT: testb $1, %sil
1669-
; X64-SLM-NEXT: cmoveq %rcx, %rax
1670-
; X64-SLM-NEXT: retq
1671-
;
1672-
; X64-HSW-NOOPT-LABEL: PR111325:
1673-
; X64-HSW-NOOPT: # %bb.0: # %entry
1674-
; X64-HSW-NOOPT-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1675-
; X64-HSW-NOOPT-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1676-
; X64-HSW-NOOPT-NEXT: imull %edi, %eax
1677-
; X64-HSW-NOOPT-NEXT: testb $1, %sil
1678-
; X64-HSW-NOOPT-NEXT: cmoveq %rcx, %rax
1679-
; X64-HSW-NOOPT-NEXT: retq
1680-
;
1681-
; X64-JAG-NOOPT-LABEL: PR111325:
1682-
; X64-JAG-NOOPT: # %bb.0: # %entry
1683-
; X64-JAG-NOOPT-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1684-
; X64-JAG-NOOPT-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1685-
; X64-JAG-NOOPT-NEXT: imull %edi, %eax
1686-
; X64-JAG-NOOPT-NEXT: testb $1, %sil
1687-
; X64-JAG-NOOPT-NEXT: cmoveq %rcx, %rax
1688-
; X64-JAG-NOOPT-NEXT: retq
1689-
;
1690-
; X64-SLM-NOOPT-LABEL: PR111325:
1691-
; X64-SLM-NOOPT: # %bb.0: # %entry
1692-
; X64-SLM-NOOPT-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1693-
; X64-SLM-NOOPT-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
1694-
; X64-SLM-NOOPT-NEXT: imull %edi, %eax
1695-
; X64-SLM-NOOPT-NEXT: testb $1, %sil
1696-
; X64-SLM-NOOPT-NEXT: cmoveq %rcx, %rax
1697-
; X64-SLM-NOOPT-NEXT: retq
1645+
; X64-LABEL: PR111325:
1646+
; X64: # %bb.0: # %entry
1647+
; X64-NEXT: negl %edi
1648+
; X64-NEXT: testb $1, %sil
1649+
; X64-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
1650+
; X64-NEXT: cmovneq %rdi, %rax
1651+
; X64-NEXT: retq
16981652
entry:
16991653
%mul = mul i64 %a0, 4294967295
17001654
%mask = and i64 %mul, 4294967295

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