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Pre-commit some PowerPC test cases
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3 files changed

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‎llvm/test/CodeGen/PowerPC/fp-classify.ll‎

Lines changed: 132 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -106,21 +106,141 @@ entry:
106106
ret i1 %cmpinf
107107
}
108108

109+
define zeroext i1 @abs_isinfornanf(float %x) {
110+
; P8-LABEL: abs_isinfornanf:
111+
; P8: # %bb.0: # %entry
112+
; P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
113+
; P8-NEXT: xsabsdp 0, 1
114+
; P8-NEXT: lfs 1, .LCPI3_0@toc@l(3)
115+
; P8-NEXT: li 3, 1
116+
; P8-NEXT: fcmpu 0, 0, 1
117+
; P8-NEXT: isellt 3, 0, 3
118+
; P8-NEXT: blr
119+
;
120+
; P9-LABEL: abs_isinfornanf:
121+
; P9: # %bb.0: # %entry
122+
; P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
123+
; P9-NEXT: xsabsdp 0, 1
124+
; P9-NEXT: lfs 1, .LCPI3_0@toc@l(3)
125+
; P9-NEXT: li 3, 1
126+
; P9-NEXT: fcmpu 0, 0, 1
127+
; P9-NEXT: isellt 3, 0, 3
128+
; P9-NEXT: blr
129+
entry:
130+
%0 = tail call float @llvm.fabs.f32(float %x)
131+
%cmpinf = fcmp ueq float %0, 0x7FF0000000000000
132+
ret i1 %cmpinf
133+
}
134+
135+
define zeroext i1 @abs_isinfornan(double %x) {
136+
; P8-LABEL: abs_isinfornan:
137+
; P8: # %bb.0: # %entry
138+
; P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha
139+
; P8-NEXT: xsabsdp 0, 1
140+
; P8-NEXT: lfs 1, .LCPI4_0@toc@l(3)
141+
; P8-NEXT: li 3, 1
142+
; P8-NEXT: fcmpu 0, 0, 1
143+
; P8-NEXT: isellt 3, 0, 3
144+
; P8-NEXT: blr
145+
;
146+
; P9-LABEL: abs_isinfornan:
147+
; P9: # %bb.0: # %entry
148+
; P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha
149+
; P9-NEXT: xsabsdp 0, 1
150+
; P9-NEXT: lfs 1, .LCPI4_0@toc@l(3)
151+
; P9-NEXT: li 3, 1
152+
; P9-NEXT: fcmpu 0, 0, 1
153+
; P9-NEXT: isellt 3, 0, 3
154+
; P9-NEXT: blr
155+
entry:
156+
%0 = tail call double @llvm.fabs.f64(double %x)
157+
%cmpinf = fcmp ueq double %0, 0x7FF0000000000000
158+
ret i1 %cmpinf
159+
}
160+
161+
define zeroext i1 @abs_isinfornanq(fp128 %x) {
162+
; P8-LABEL: abs_isinfornanq:
163+
; P8: # %bb.0: # %entry
164+
; P8-NEXT: mflr 0
165+
; P8-NEXT: stdu 1, -112(1)
166+
; P8-NEXT: std 0, 128(1)
167+
; P8-NEXT: .cfi_def_cfa_offset 112
168+
; P8-NEXT: .cfi_offset lr, 16
169+
; P8-NEXT: .cfi_offset r30, -16
170+
; P8-NEXT: .cfi_offset v30, -48
171+
; P8-NEXT: .cfi_offset v31, -32
172+
; P8-NEXT: li 3, 64
173+
; P8-NEXT: xxswapd 0, 34
174+
; P8-NEXT: std 30, 96(1) # 8-byte Folded Spill
175+
; P8-NEXT: stvx 30, 1, 3 # 16-byte Folded Spill
176+
; P8-NEXT: li 3, 80
177+
; P8-NEXT: stvx 31, 1, 3 # 16-byte Folded Spill
178+
; P8-NEXT: addi 3, 1, 48
179+
; P8-NEXT: stxvd2x 0, 0, 3
180+
; P8-NEXT: lbz 4, 63(1)
181+
; P8-NEXT: clrlwi 4, 4, 25
182+
; P8-NEXT: stb 4, 63(1)
183+
; P8-NEXT: lxvd2x 0, 0, 3
184+
; P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha
185+
; P8-NEXT: addi 3, 3, .LCPI5_0@toc@l
186+
; P8-NEXT: xxswapd 63, 0
187+
; P8-NEXT: lxvd2x 0, 0, 3
188+
; P8-NEXT: vmr 2, 31
189+
; P8-NEXT: xxswapd 62, 0
190+
; P8-NEXT: vmr 3, 30
191+
; P8-NEXT: bl __eqkf2
192+
; P8-NEXT: nop
193+
; P8-NEXT: cntlzw 3, 3
194+
; P8-NEXT: vmr 2, 31
195+
; P8-NEXT: vmr 3, 30
196+
; P8-NEXT: srwi 30, 3, 5
197+
; P8-NEXT: bl __unordkf2
198+
; P8-NEXT: nop
199+
; P8-NEXT: cntlzw 3, 3
200+
; P8-NEXT: li 4, 80
201+
; P8-NEXT: lvx 31, 1, 4 # 16-byte Folded Reload
202+
; P8-NEXT: li 4, 64
203+
; P8-NEXT: srwi 3, 3, 5
204+
; P8-NEXT: lvx 30, 1, 4 # 16-byte Folded Reload
205+
; P8-NEXT: xori 3, 3, 1
206+
; P8-NEXT: or 3, 3, 30
207+
; P8-NEXT: ld 30, 96(1) # 8-byte Folded Reload
208+
; P8-NEXT: addi 1, 1, 112
209+
; P8-NEXT: ld 0, 16(1)
210+
; P8-NEXT: mtlr 0
211+
; P8-NEXT: blr
212+
;
213+
; P9-LABEL: abs_isinfornanq:
214+
; P9: # %bb.0: # %entry
215+
; P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha
216+
; P9-NEXT: xsabsqp 2, 2
217+
; P9-NEXT: addi 3, 3, .LCPI5_0@toc@l
218+
; P9-NEXT: lxv 35, 0(3)
219+
; P9-NEXT: li 3, 1
220+
; P9-NEXT: xscmpuqp 0, 2, 3
221+
; P9-NEXT: isellt 3, 0, 3
222+
; P9-NEXT: blr
223+
entry:
224+
%0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
225+
%cmpinf = fcmp ueq fp128 %0, 0xL00000000000000007FFF000000000000
226+
ret i1 %cmpinf
227+
}
228+
109229
define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {
110230
; P8-LABEL: abs_isinfv4f32:
111231
; P8: # %bb.0: # %entry
112-
; P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
232+
; P8-NEXT: addis 3, 2, .LCPI6_0@toc@ha
113233
; P8-NEXT: xvabssp 0, 34
114-
; P8-NEXT: addi 3, 3, .LCPI3_0@toc@l
234+
; P8-NEXT: addi 3, 3, .LCPI6_0@toc@l
115235
; P8-NEXT: lxvd2x 1, 0, 3
116236
; P8-NEXT: xvcmpeqsp 34, 0, 1
117237
; P8-NEXT: blr
118238
;
119239
; P9-LABEL: abs_isinfv4f32:
120240
; P9: # %bb.0: # %entry
121-
; P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
241+
; P9-NEXT: addis 3, 2, .LCPI6_0@toc@ha
122242
; P9-NEXT: xvabssp 0, 34
123-
; P9-NEXT: addi 3, 3, .LCPI3_0@toc@l
243+
; P9-NEXT: addi 3, 3, .LCPI6_0@toc@l
124244
; P9-NEXT: lxv 1, 0(3)
125245
; P9-NEXT: xvcmpeqsp 34, 0, 1
126246
; P9-NEXT: blr
@@ -133,18 +253,18 @@ entry:
133253
define <2 x i1> @abs_isinfv2f64(<2 x double> %x) {
134254
; P8-LABEL: abs_isinfv2f64:
135255
; P8: # %bb.0: # %entry
136-
; P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha
256+
; P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha
137257
; P8-NEXT: xvabsdp 0, 34
138-
; P8-NEXT: addi 3, 3, .LCPI4_0@toc@l
258+
; P8-NEXT: addi 3, 3, .LCPI7_0@toc@l
139259
; P8-NEXT: lxvd2x 1, 0, 3
140260
; P8-NEXT: xvcmpeqdp 34, 0, 1
141261
; P8-NEXT: blr
142262
;
143263
; P9-LABEL: abs_isinfv2f64:
144264
; P9: # %bb.0: # %entry
145-
; P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha
265+
; P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha
146266
; P9-NEXT: xvabsdp 0, 34
147-
; P9-NEXT: addi 3, 3, .LCPI4_0@toc@l
267+
; P9-NEXT: addi 3, 3, .LCPI7_0@toc@l
148268
; P9-NEXT: lxv 1, 0(3)
149269
; P9-NEXT: xvcmpeqdp 34, 0, 1
150270
; P9-NEXT: blr
@@ -208,8 +328,8 @@ define zeroext i1 @iszeroq(fp128 %x) {
208328
; P8-NEXT: std 0, 48(1)
209329
; P8-NEXT: .cfi_def_cfa_offset 32
210330
; P8-NEXT: .cfi_offset lr, 16
211-
; P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha
212-
; P8-NEXT: addi 3, 3, .LCPI7_0@toc@l
331+
; P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha
332+
; P8-NEXT: addi 3, 3, .LCPI10_0@toc@l
213333
; P8-NEXT: lxvd2x 0, 0, 3
214334
; P8-NEXT: xxswapd 35, 0
215335
; P8-NEXT: bl __eqkf2
@@ -223,9 +343,9 @@ define zeroext i1 @iszeroq(fp128 %x) {
223343
;
224344
; P9-LABEL: iszeroq:
225345
; P9: # %bb.0: # %entry
226-
; P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha
346+
; P9-NEXT: addis 3, 2, .LCPI10_0@toc@ha
227347
; P9-NEXT: li 4, 1
228-
; P9-NEXT: addi 3, 3, .LCPI7_0@toc@l
348+
; P9-NEXT: addi 3, 3, .LCPI10_0@toc@l
229349
; P9-NEXT: lxv 35, 0(3)
230350
; P9-NEXT: li 3, 0
231351
; P9-NEXT: xscmpuqp 0, 2, 3

‎llvm/test/CodeGen/PowerPC/rldimi.ll‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2+
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s
3+
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix -mcpu=pwr8 | FileCheck %s
4+
5+
define i64 @rldimi1(i64 %a) {
6+
; CHECK-LABEL: rldimi1:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: rldimi 3, 3, 8, 0
9+
; CHECK-NEXT: blr
10+
entry:
11+
%x0 = shl i64 %a, 8
12+
%x1 = and i64 %a, 255
13+
%x2 = or i64 %x0, %x1
14+
ret i64 %x2
15+
}
16+
17+
define i64 @rldimi2(i64 %a) {
18+
; CHECK-LABEL: rldimi2:
19+
; CHECK: # %bb.0: # %entry
20+
; CHECK-NEXT: mr 4, 3
21+
; CHECK-NEXT: rlwimi 4, 3, 8, 16, 23
22+
; CHECK-NEXT: rlwimi 4, 3, 16, 8, 15
23+
; CHECK-NEXT: rldimi 4, 3, 24, 0
24+
; CHECK-NEXT: mr 3, 4
25+
; CHECK-NEXT: blr
26+
entry:
27+
%x0 = shl i64 %a, 8
28+
%x1 = and i64 %a, 255
29+
%x2 = or i64 %x0, %x1
30+
%x3 = shl i64 %x2, 16
31+
%x4 = and i64 %x2, 65535
32+
%x5 = or i64 %x3, %x4
33+
ret i64 %x5
34+
}
35+
36+
define i64 @rldimi3(i64 %a) {
37+
; CHECK-LABEL: rldimi3:
38+
; CHECK: # %bb.0: # %entry
39+
; CHECK-NEXT: rotldi 4, 3, 32
40+
; CHECK-NEXT: rlwimi 4, 3, 0, 24, 31
41+
; CHECK-NEXT: rlwimi 4, 3, 8, 16, 23
42+
; CHECK-NEXT: rlwimi 4, 3, 16, 8, 15
43+
; CHECK-NEXT: rlwimi 4, 3, 24, 0, 7
44+
; CHECK-NEXT: rldimi 4, 3, 40, 16
45+
; CHECK-NEXT: rldimi 4, 3, 48, 8
46+
; CHECK-NEXT: rldimi 4, 3, 56, 0
47+
; CHECK-NEXT: mr 3, 4
48+
; CHECK-NEXT: blr
49+
entry:
50+
%0 = shl i64 %a, 8
51+
%1 = and i64 %a, 255
52+
%2 = or i64 %0, %1
53+
%3 = shl i64 %2, 16
54+
%4 = and i64 %2, 65535
55+
%5 = or i64 %3, %4
56+
%6 = shl i64 %5, 32
57+
%7 = and i64 %5, 4294967295
58+
%8 = or i64 %6, %7
59+
ret i64 %8
60+
}

‎llvm/test/CodeGen/PowerPC/setcc-to-sub.ll‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,101 @@ entry:
8989
ret i1 %cmp.i5
9090
}
9191

92+
define zeroext i1 @test5(i64 %a) {
93+
; CHECK-LABEL: test5:
94+
; CHECK: # %bb.0: # %entry
95+
; CHECK-NEXT: li 4, -1
96+
; CHECK-NEXT: addis 3, 3, -32768
97+
; CHECK-NEXT: rldic 4, 4, 32, 0
98+
; CHECK-NEXT: subc 4, 3, 4
99+
; CHECK-NEXT: subfe 3, 3, 3
100+
; CHECK-NEXT: neg 3, 3
101+
; CHECK-NEXT: blr
102+
entry:
103+
%0 = add i64 %a, -2147483648
104+
%cmp = icmp ult i64 %0, -4294967296
105+
ret i1 %cmp
106+
}
107+
108+
define zeroext i1 @test6(i64 %a) {
109+
; CHECK-LABEL: test6:
110+
; CHECK: # %bb.0: # %entry
111+
; CHECK-NEXT: addi 3, 3, -32768
112+
; CHECK-NEXT: lis 4, -1
113+
; CHECK-NEXT: subc 4, 3, 4
114+
; CHECK-NEXT: subfe 3, 3, 3
115+
; CHECK-NEXT: neg 3, 3
116+
; CHECK-NEXT: blr
117+
entry:
118+
%0 = add i64 %a, -32768
119+
%cmp = icmp ult i64 %0, -65536
120+
ret i1 %cmp
121+
}
122+
123+
define zeroext i1 @test7(i64 %a) {
124+
; CHECK-LABEL: test7:
125+
; CHECK: # %bb.0: # %entry
126+
; CHECK-NEXT: addi 3, 3, -128
127+
; CHECK-NEXT: li 4, -256
128+
; CHECK-NEXT: subc 4, 3, 4
129+
; CHECK-NEXT: subfe 3, 3, 3
130+
; CHECK-NEXT: neg 3, 3
131+
; CHECK-NEXT: blr
132+
entry:
133+
%0 = add i64 %a, -128
134+
%cmp = icmp ult i64 %0, -256
135+
ret i1 %cmp
136+
}
137+
138+
define zeroext i1 @test8(i32 %a) {
139+
; CHECK-LABEL: test8:
140+
; CHECK: # %bb.0: # %entry
141+
; CHECK-NEXT: addi 3, 3, -32768
142+
; CHECK-NEXT: lis 4, -1
143+
; CHECK-NEXT: rlwinm 3, 3, 16, 16, 31
144+
; CHECK-NEXT: ori 4, 4, 1
145+
; CHECK-NEXT: add 3, 3, 4
146+
; CHECK-NEXT: rldicl 3, 3, 1, 63
147+
; CHECK-NEXT: blr
148+
entry:
149+
%0 = add i32 %a, -32768
150+
%cmp = icmp ult i32 %0, -65536
151+
ret i1 %cmp
152+
}
153+
154+
define zeroext i1 @test9(i32 %a) {
155+
; CHECK-LABEL: test9:
156+
; CHECK: # %bb.0: # %entry
157+
; CHECK-NEXT: lis 4, -256
158+
; CHECK-NEXT: addi 3, 3, -128
159+
; CHECK-NEXT: ori 4, 4, 1
160+
; CHECK-NEXT: clrldi 3, 3, 32
161+
; CHECK-NEXT: rldic 4, 4, 8, 0
162+
; CHECK-NEXT: add 3, 3, 4
163+
; CHECK-NEXT: rldicl 3, 3, 1, 63
164+
; CHECK-NEXT: blr
165+
entry:
166+
%0 = add i32 %a, -128
167+
%cmp = icmp ult i32 %0, -256
168+
ret i1 %cmp
169+
}
170+
171+
define zeroext i1 @test10(i16 %a) {
172+
; CHECK-LABEL: test10:
173+
; CHECK: # %bb.0: # %entry
174+
; CHECK-NEXT: addi 3, 3, -128
175+
; CHECK-NEXT: lis 4, -1
176+
; CHECK-NEXT: clrlwi 3, 3, 16
177+
; CHECK-NEXT: ori 4, 4, 256
178+
; CHECK-NEXT: add 3, 3, 4
179+
; CHECK-NEXT: rldicl 3, 3, 1, 63
180+
; CHECK-NEXT: blr
181+
entry:
182+
%0 = add i16 %a, -128
183+
%cmp = icmp ult i16 %0, -256
184+
ret i1 %cmp
185+
}
186+
92187
!1 = !{!2, !2, i64 0}
93188
!2 = !{!"int", !3, i64 0}
94189
!3 = !{!"omnipotent char", !4, i64 0}

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