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Revert "[Clang][NEON] Add neon target guard to intrinsics" (#99864)
Reverts #98624
1 parent 15b41d2 commit c1622ca

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4 files changed

+36
-70
lines changed

4 files changed

+36
-70
lines changed

‎clang/include/clang/Basic/arm_neon.td

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ def SPLATQ : WInst<"splat_laneq", ".(!Q)I",
289289
"UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
290290
let isLaneQ = 1;
291291
}
292-
let TargetGuard = "bf16,neon" in {
292+
let TargetGuard = "bf16" in {
293293
def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb">;
294294
def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
295295
let isLaneQ = 1;
@@ -323,7 +323,7 @@ def VMLSL : SOpInst<"vmlsl", "(>Q)(>Q)..", "csiUcUsUi", OP_MLSL>;
323323
def VQDMULH : SInst<"vqdmulh", "...", "siQsQi">;
324324
def VQRDMULH : SInst<"vqrdmulh", "...", "siQsQi">;
325325

326-
let TargetGuard = "v8.1a,neon" in {
326+
let TargetGuard = "v8.1a" in {
327327
def VQRDMLAH : SInst<"vqrdmlah", "....", "siQsQi">;
328328
def VQRDMLSH : SInst<"vqrdmlsh", "....", "siQsQi">;
329329
}
@@ -614,7 +614,7 @@ def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
614614
def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
615615
}
616616

617-
let TargetGuard = "v8.1a,neon" in {
617+
let TargetGuard = "v8.1a" in {
618618
def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "...qI", "siQsQi", OP_QRDMLAH_LN>;
619619
def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "...qI", "siQsQi", OP_QRDMLSH_LN>;
620620
}
@@ -957,7 +957,7 @@ def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "(>Q)(>Q)QQ", "si", OP_QDMLALHi>;
957957
def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLALHi_N>;
958958
def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "(>Q)(>Q)QQ", "si", OP_QDMLSLHi>;
959959
def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLSLHi_N>;
960-
let TargetGuard = "aes,neon" in {
960+
let TargetGuard = "aes" in {
961961
def VMULL_P64 : SInst<"vmull", "(1>)11", "Pl">;
962962
def VMULL_HIGH_P64 : SOpInst<"vmull_high", "(1>)..", "HPl", OP_MULLHi_P64>;
963963
}
@@ -1091,7 +1091,7 @@ let isLaneQ = 1 in {
10911091
def VQDMULH_LANEQ : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
10921092
def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
10931093
}
1094-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a,neon" in {
1094+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a" in {
10951095
def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN> {
10961096
let isLaneQ = 1;
10971097
}
@@ -1122,14 +1122,14 @@ def VEXT_A64 : WInst<"vext", "...I", "dQdPlQPl">;
11221122

11231123
////////////////////////////////////////////////////////////////////////////////
11241124
// Crypto
1125-
let ArchGuard = "__ARM_ARCH >= 8", TargetGuard = "aes,neon" in {
1125+
let ArchGuard = "__ARM_ARCH >= 8", TargetGuard = "aes" in {
11261126
def AESE : SInst<"vaese", "...", "QUc">;
11271127
def AESD : SInst<"vaesd", "...", "QUc">;
11281128
def AESMC : SInst<"vaesmc", "..", "QUc">;
11291129
def AESIMC : SInst<"vaesimc", "..", "QUc">;
11301130
}
11311131

1132-
let ArchGuard = "__ARM_ARCH >= 8", TargetGuard = "sha2,neon" in {
1132+
let ArchGuard = "__ARM_ARCH >= 8", TargetGuard = "sha2" in {
11331133
def SHA1H : SInst<"vsha1h", "11", "Ui">;
11341134
def SHA1SU1 : SInst<"vsha1su1", "...", "QUi">;
11351135
def SHA256SU0 : SInst<"vsha256su0", "...", "QUi">;
@@ -1143,7 +1143,7 @@ def SHA256H2 : SInst<"vsha256h2", "....", "QUi">;
11431143
def SHA256SU1 : SInst<"vsha256su1", "....", "QUi">;
11441144
}
11451145

1146-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3,neon" in {
1146+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3" in {
11471147
def BCAX : SInst<"vbcax", "....", "QUcQUsQUiQUlQcQsQiQl">;
11481148
def EOR3 : SInst<"veor3", "....", "QUcQUsQUiQUlQcQsQiQl">;
11491149
def RAX1 : SInst<"vrax1", "...", "QUl">;
@@ -1153,14 +1153,14 @@ def XAR : SInst<"vxar", "...I", "QUl">;
11531153
}
11541154
}
11551155

1156-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3,neon" in {
1156+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3" in {
11571157
def SHA512SU0 : SInst<"vsha512su0", "...", "QUl">;
11581158
def SHA512su1 : SInst<"vsha512su1", "....", "QUl">;
11591159
def SHA512H : SInst<"vsha512h", "....", "QUl">;
11601160
def SHA512H2 : SInst<"vsha512h2", "....", "QUl">;
11611161
}
11621162

1163-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4,neon" in {
1163+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4" in {
11641164
def SM3SS1 : SInst<"vsm3ss1", "....", "QUi">;
11651165
def SM3TT1A : SInst<"vsm3tt1a", "....I", "QUi">;
11661166
def SM3TT1B : SInst<"vsm3tt1b", "....I", "QUi">;
@@ -1170,7 +1170,7 @@ def SM3PARTW1 : SInst<"vsm3partw1", "....", "QUi">;
11701170
def SM3PARTW2 : SInst<"vsm3partw2", "....", "QUi">;
11711171
}
11721172

1173-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4,neon" in {
1173+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4" in {
11741174
def SM4E : SInst<"vsm4e", "...", "QUi">;
11751175
def SM4EKEY : SInst<"vsm4ekey", "...", "QUi">;
11761176
}
@@ -1227,7 +1227,7 @@ def FRINTZ_S64 : SInst<"vrnd", "..", "dQd">;
12271227
def FRINTI_S64 : SInst<"vrndi", "..", "dQd">;
12281228
}
12291229

1230-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.5a,neon" in {
1230+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.5a" in {
12311231
def FRINT32X_S32 : SInst<"vrnd32x", "..", "fQf">;
12321232
def FRINT32Z_S32 : SInst<"vrnd32z", "..", "fQf">;
12331233
def FRINT64X_S32 : SInst<"vrnd64x", "..", "fQf">;
@@ -1401,7 +1401,7 @@ def SCALAR_SQDMULH : SInst<"vqdmulh", "111", "SsSi">;
14011401
// Scalar Integer Saturating Rounding Doubling Multiply Half High
14021402
def SCALAR_SQRDMULH : SInst<"vqrdmulh", "111", "SsSi">;
14031403

1404-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a,neon" in {
1404+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a" in {
14051405
////////////////////////////////////////////////////////////////////////////////
14061406
// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
14071407
def SCALAR_SQRDMLAH : SInst<"vqrdmlah", "1111", "SsSi">;
@@ -1632,7 +1632,7 @@ def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "11QI", "SsSi", OP_SCALAR_
16321632
let isLaneQ = 1;
16331633
}
16341634

1635-
let TargetGuard = "v8.1a,neon" in {
1635+
let TargetGuard = "v8.1a" in {
16361636
// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
16371637
def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "111.I", "SsSi", OP_SCALAR_QRDMLAH_LN>;
16381638
def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLAH_LN> {
@@ -1654,7 +1654,7 @@ def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcS
16541654
} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)"
16551655

16561656
// ARMv8.2-A FP16 vector intrinsics for A32/A64.
1657-
let TargetGuard = "fullfp16,neon" in {
1657+
let TargetGuard = "fullfp16" in {
16581658

16591659
// ARMv8.2-A FP16 one-operand vector intrinsics.
16601660

@@ -1679,7 +1679,7 @@ let TargetGuard = "fullfp16,neon" in {
16791679
def VCVTP_U16 : SInst<"vcvtp_u16", "U.", "hQh">;
16801680

16811681
// Vector rounding
1682-
let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)", TargetGuard = "fullfp16,neon" in {
1682+
let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)", TargetGuard = "fullfp16" in {
16831683
def FRINTZH : SInst<"vrnd", "..", "hQh">;
16841684
def FRINTNH : SInst<"vrndn", "..", "hQh">;
16851685
def FRINTAH : SInst<"vrnda", "..", "hQh">;
@@ -1728,7 +1728,7 @@ let TargetGuard = "fullfp16,neon" in {
17281728
// Max/Min
17291729
def VMAXH : SInst<"vmax", "...", "hQh">;
17301730
def VMINH : SInst<"vmin", "...", "hQh">;
1731-
let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)", TargetGuard = "fullfp16,neon" in {
1731+
let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)", TargetGuard = "fullfp16" in {
17321732
def FMAXNMH : SInst<"vmaxnm", "...", "hQh">;
17331733
def FMINNMH : SInst<"vminnm", "...", "hQh">;
17341734
}
@@ -1775,7 +1775,7 @@ def VEXTH : WInst<"vext", "...I", "hQh">;
17751775
def VREV64H : WOpInst<"vrev64", "..", "hQh", OP_REV64>;
17761776

17771777
// ARMv8.2-A FP16 vector intrinsics for A64 only.
1778-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fullfp16,neon" in {
1778+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fullfp16" in {
17791779

17801780
// Vector rounding
17811781
def FRINTIH : SInst<"vrndi", "..", "hQh">;
@@ -1872,19 +1872,19 @@ let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
18721872
}
18731873

18741874
// v8.2-A dot product instructions.
1875-
let TargetGuard = "dotprod,neon" in {
1875+
let TargetGuard = "dotprod" in {
18761876
def DOT : SInst<"vdot", "..(<<)(<<)", "iQiUiQUi">;
18771877
def DOT_LANE : SOpInst<"vdot_lane", "..(<<)(<<q)I", "iUiQiQUi", OP_DOT_LN>;
18781878
}
1879-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "dotprod,neon" in {
1879+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "dotprod" in {
18801880
// Variants indexing into a 128-bit vector are A64 only.
18811881
def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ> {
18821882
let isLaneQ = 1;
18831883
}
18841884
}
18851885

18861886
// v8.2-A FP16 fused multiply-add long instructions.
1887-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fp16fml,neon" in {
1887+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fp16fml" in {
18881888
def VFMLAL_LOW : SInst<"vfmlal_low", ">>..", "hQh">;
18891889
def VFMLSL_LOW : SInst<"vfmlsl_low", ">>..", "hQh">;
18901890
def VFMLAL_HIGH : SInst<"vfmlal_high", ">>..", "hQh">;
@@ -1909,7 +1909,7 @@ let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "f
19091909
}
19101910
}
19111911

1912-
let TargetGuard = "i8mm,neon" in {
1912+
let TargetGuard = "i8mm" in {
19131913
def VMMLA : SInst<"vmmla", "..(<<)(<<)", "QUiQi">;
19141914
def VUSMMLA : SInst<"vusmmla", "..(<<U)(<<)", "Qi">;
19151915

@@ -1926,7 +1926,7 @@ let TargetGuard = "i8mm,neon" in {
19261926
}
19271927
}
19281928

1929-
let TargetGuard = "bf16,neon" in {
1929+
let TargetGuard = "bf16" in {
19301930
def VDOT_BF : SInst<"vbfdot", "..BB", "fQf">;
19311931
def VDOT_LANE_BF : SOpInst<"vbfdot_lane", "..B(Bq)I", "fQf", OP_BFDOT_LN>;
19321932
def VDOT_LANEQ_BF : SOpInst<"vbfdot_laneq", "..B(BQ)I", "fQf", OP_BFDOT_LNQ> {
@@ -1970,31 +1970,31 @@ multiclass VCMLA_ROTS<string type, string lanety, string laneqty> {
19701970
}
19711971

19721972
// v8.3-A Vector complex addition intrinsics
1973-
let TargetGuard = "v8.3a,fullfp16,neon" in {
1973+
let TargetGuard = "v8.3a,fullfp16" in {
19741974
def VCADD_ROT90_FP16 : SInst<"vcadd_rot90", "...", "h">;
19751975
def VCADD_ROT270_FP16 : SInst<"vcadd_rot270", "...", "h">;
19761976
def VCADDQ_ROT90_FP16 : SInst<"vcaddq_rot90", "QQQ", "h">;
19771977
def VCADDQ_ROT270_FP16 : SInst<"vcaddq_rot270", "QQQ", "h">;
19781978

19791979
defm VCMLA_FP16 : VCMLA_ROTS<"h", "uint32x2_t", "uint32x4_t">;
19801980
}
1981-
let TargetGuard = "v8.3a,neon" in {
1981+
let TargetGuard = "v8.3a" in {
19821982
def VCADD_ROT90 : SInst<"vcadd_rot90", "...", "f">;
19831983
def VCADD_ROT270 : SInst<"vcadd_rot270", "...", "f">;
19841984
def VCADDQ_ROT90 : SInst<"vcaddq_rot90", "QQQ", "f">;
19851985
def VCADDQ_ROT270 : SInst<"vcaddq_rot270", "QQQ", "f">;
19861986

19871987
defm VCMLA_F32 : VCMLA_ROTS<"f", "uint64x1_t", "uint64x2_t">;
19881988
}
1989-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.3a,neon" in {
1989+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.3a" in {
19901990
def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
19911991
def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
19921992

19931993
defm VCMLA_FP64 : VCMLA_ROTS<"d", "uint64x2_t", "uint64x2_t">;
19941994
}
19951995

19961996
// V8.2-A BFloat intrinsics
1997-
let TargetGuard = "bf16,neon" in {
1997+
let TargetGuard = "bf16" in {
19981998
def VCREATE_BF : NoTestOpInst<"vcreate", ".(IU>)", "b", OP_CAST> {
19991999
let BigEndianSafe = 1;
20002000
}
@@ -2058,14 +2058,14 @@ let TargetGuard = "bf16,neon" in {
20582058
def SCALAR_CVT_F32_BF16 : SOpInst<"vcvtah_f32", "(1F>)(1!)", "b", OP_CVT_F32_BF16>;
20592059
}
20602060

2061-
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16,neon" in {
2061+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16" in {
20622062
def VCVT_BF16_F32_A32_INTERNAL : WInst<"__a32_vcvt_bf16", "BQ", "f">;
20632063
def VCVT_BF16_F32_A32 : SOpInst<"vcvt_bf16", "BQ", "f", OP_VCVT_BF16_F32_A32>;
20642064
def VCVT_LOW_BF16_F32_A32 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A32>;
20652065
def VCVT_HIGH_BF16_F32_A32 : SOpInst<"vcvt_high_bf16", "BBQ", "Qf", OP_VCVT_BF16_F32_HI_A32>;
20662066
}
20672067

2068-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16,neon" in {
2068+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16" in {
20692069
def VCVT_LOW_BF16_F32_A64_INTERNAL : WInst<"__a64_vcvtq_low_bf16", "BQ", "Hf">;
20702070
def VCVT_LOW_BF16_F32_A64 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A64>;
20712071
def VCVT_HIGH_BF16_F32_A64 : SInst<"vcvt_high_bf16", "BBQ", "Qf">;
@@ -2077,22 +2077,22 @@ let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "b
20772077
def COPYQ_LANEQ_BF16 : IOpInst<"vcopy_laneq", "..I.I", "Qb", OP_COPY_LN>;
20782078
}
20792079

2080-
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16,neon" in {
2080+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16" in {
20812081
let BigEndianSafe = 1 in {
20822082
defm VREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
20832083
"csilUcUsUiUlhfPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQPcQPsQPl", "bQb">;
20842084
}
20852085
}
20862086

2087-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16,neon" in {
2087+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16" in {
20882088
let BigEndianSafe = 1 in {
20892089
defm VVREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
20902090
"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", "bQb">;
20912091
}
20922092
}
20932093

20942094
// v8.9a/v9.4a LRCPC3 intrinsics
2095-
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "rcpc3,neon" in {
2095+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "rcpc3" in {
20962096
def VLDAP1_LANE : WInst<"vldap1_lane", ".(c*!).I", "QUlQlUlldQdPlQPl">;
20972097
def VSTL1_LANE : WInst<"vstl1_lane", "v*(.!)I", "QUlQlUlldQdPlQPl">;
20982098
}

‎clang/include/clang/Basic/arm_neon_incl.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ class Inst <string n, string p, string t, Operation o> {
265265
string Prototype = p;
266266
string Types = t;
267267
string ArchGuard = "";
268-
string TargetGuard = "neon";
268+
string TargetGuard = "";
269269

270270
Operation Operation = o;
271271
bit BigEndianSafe = 0;

‎clang/test/Sema/aarch64-neon-without-target-feature.cpp

Lines changed: 0 additions & 34 deletions
This file was deleted.

‎clang/utils/TableGen/NeonEmitter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -952,7 +952,7 @@ std::string Intrinsic::getInstTypeCode(Type T, ClassKind CK) const {
952952
char typeCode = '\0';
953953
bool printNumber = true;
954954

955-
if (CK == ClassB && TargetGuard == "neon")
955+
if (CK == ClassB && TargetGuard == "")
956956
return "";
957957

958958
if (T.isBFloat16())
@@ -976,7 +976,7 @@ std::string Intrinsic::getInstTypeCode(Type T, ClassKind CK) const {
976976
break;
977977
}
978978
}
979-
if (CK == ClassB && TargetGuard == "neon") {
979+
if (CK == ClassB && TargetGuard == "") {
980980
typeCode = '\0';
981981
}
982982

@@ -1078,7 +1078,7 @@ std::string Intrinsic::mangleName(std::string Name, ClassKind LocalCK) const {
10781078
S += "_" + getInstTypeCode(InBaseType, LocalCK);
10791079
}
10801080

1081-
if (LocalCK == ClassB && TargetGuard == "neon")
1081+
if (LocalCK == ClassB && TargetGuard == "")
10821082
S += "_v";
10831083

10841084
// Insert a 'q' before the first '_' character so that it ends up before

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