Skip to content

Commit ba3ef33

Browse files
mgudimmgudim
authored
[RISCV][GlobalISel] Zbkb support for G_BSWAP (#77050)
This instructions is legal in the presence of Zbkb extension.
1 parent 1637c07 commit ba3ef33

File tree

5 files changed

+77
-71
lines changed

5 files changed

+77
-71
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
113113
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();
114114

115115
auto &BSWAPActions = getActionDefinitionsBuilder(G_BSWAP);
116-
if (ST.hasStdExtZbb())
116+
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb())
117117
BSWAPActions.legalFor({sXLen}).clampScalar(0, sXLen, sXLen);
118118
else
119119
BSWAPActions.maxScalar(0, sXLen).lower();

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,20 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \
3-
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
4-
# RUN: | FileCheck -check-prefix=RV32I %s
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \
5+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
56

67
---
78
name: bswap_s32
89
legalized: true
910
regBankSelected: true
1011
body: |
1112
bb.0.entry:
12-
; RV32I-LABEL: name: bswap_s32
13-
; RV32I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14-
; RV32I-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
15-
; RV32I-NEXT: $x10 = COPY [[REV8_RV32_]]
16-
; RV32I-NEXT: PseudoRET implicit $x10
13+
; CHECK-LABEL: name: bswap_s32
14+
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
15+
; CHECK-NEXT: [[REV8_RV32_:%[0-9]+]]:gpr = REV8_RV32 [[COPY]]
16+
; CHECK-NEXT: $x10 = COPY [[REV8_RV32_]]
17+
; CHECK-NEXT: PseudoRET implicit $x10
1718
%0:gprb(s32) = COPY $x10
1819
%1:gprb(s32) = G_BSWAP %0
1920
$x10 = COPY %1(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,20 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
3-
# RUN: -simplify-mir -verify-machineinstrs %s -o - \
4-
# RUN: | FileCheck -check-prefix=RV64I %s
3+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4+
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
5+
# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
56

67
---
78
name: bswap_s64
89
legalized: true
910
regBankSelected: true
1011
body: |
1112
bb.0.entry:
12-
; RV64I-LABEL: name: bswap_s64
13-
; RV64I: [[COPY:%[0-9]+]]:gpr = COPY $x10
14-
; RV64I-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
15-
; RV64I-NEXT: $x10 = COPY [[REV8_RV64_]]
16-
; RV64I-NEXT: PseudoRET implicit $x10
13+
; CHECK-LABEL: name: bswap_s64
14+
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x10
15+
; CHECK-NEXT: [[REV8_RV64_:%[0-9]+]]:gpr = REV8_RV64 [[COPY]]
16+
; CHECK-NEXT: $x10 = COPY [[REV8_RV64_]]
17+
; CHECK-NEXT: PseudoRET implicit $x10
1718
%0:gprb(s64) = COPY $x10
1819
%1:gprb(s64) = G_BSWAP %0
1920
$x10 = COPY %1(s64)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir‎

Lines changed: 30 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
33
# RUN: | FileCheck %s --check-prefix=RV32I
44
# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
5-
# RUN: | FileCheck %s --check-prefix=RV32ZBB
5+
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
6+
# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
7+
# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
68

79
---
810
name: bswap_i16
@@ -23,16 +25,16 @@ body: |
2325
; RV32I-NEXT: $x10 = COPY [[AND]](s32)
2426
; RV32I-NEXT: PseudoRET implicit $x10
2527
;
26-
; RV32ZBB-LABEL: name: bswap_i16
27-
; RV32ZBB: liveins: $x10
28-
; RV32ZBB-NEXT: {{ $}}
29-
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
30-
; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
31-
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
32-
; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
33-
; RV32ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
34-
; RV32ZBB-NEXT: $x10 = COPY [[LSHR]](s32)
35-
; RV32ZBB-NEXT: PseudoRET implicit $x10
28+
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16
29+
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
30+
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
31+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
32+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
33+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
34+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
35+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
36+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)
37+
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
3638
%0:_(s32) = COPY $x10
3739
%1:_(s32) = G_ASSERT_ZEXT %0, 16
3840
%2:_(s16) = G_TRUNC %1(s32)
@@ -65,13 +67,13 @@ body: |
6567
; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
6668
; RV32I-NEXT: PseudoRET implicit $x10
6769
;
68-
; RV32ZBB-LABEL: name: bswap_i32
69-
; RV32ZBB: liveins: $x10
70-
; RV32ZBB-NEXT: {{ $}}
71-
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
72-
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
73-
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
74-
; RV32ZBB-NEXT: PseudoRET implicit $x10
70+
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32
71+
; RV32ZBB_OR_RV32ZBKB: liveins: $x10
72+
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
73+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
74+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
75+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
76+
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
7577
%0:_(s32) = COPY $x10
7678
%1:_(s32) = G_BSWAP %0
7779
$x10 = COPY %1(s32)
@@ -115,16 +117,16 @@ body: |
115117
; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
116118
; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
117119
;
118-
; RV32ZBB-LABEL: name: bswap_i64
119-
; RV32ZBB: liveins: $x10, $x11
120-
; RV32ZBB-NEXT: {{ $}}
121-
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
122-
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
123-
; RV32ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
124-
; RV32ZBB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
125-
; RV32ZBB-NEXT: $x10 = COPY [[BSWAP]](s32)
126-
; RV32ZBB-NEXT: $x11 = COPY [[BSWAP1]](s32)
127-
; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11
120+
; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64
121+
; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
122+
; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
123+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
124+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
125+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
126+
; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
127+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
128+
; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)
129+
; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11
128130
%0:_(s32) = COPY $x10
129131
%1:_(s32) = COPY $x11
130132
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir‎

Lines changed: 30 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
33
# RUN: | FileCheck %s --check-prefix=RV64I
44
# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
5-
# RUN: | FileCheck %s --check-prefix=RV64ZBB
5+
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB
6+
# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=legalizer %s -o - \
7+
# RUN: | FileCheck %s --check-prefix=RV64ZBB_OR_RV64ZBKB
68

79
---
810
name: bswap_i16
@@ -27,16 +29,16 @@ body: |
2729
; RV64I-NEXT: $x10 = COPY [[AND]](s64)
2830
; RV64I-NEXT: PseudoRET implicit $x10
2931
;
30-
; RV64ZBB-LABEL: name: bswap_i16
31-
; RV64ZBB: liveins: $x10
32-
; RV64ZBB-NEXT: {{ $}}
33-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
34-
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
35-
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
36-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
37-
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
38-
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
39-
; RV64ZBB-NEXT: PseudoRET implicit $x10
32+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16
33+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
34+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
35+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
36+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16
37+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
38+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
39+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
40+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
41+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
4042
%0:_(s64) = COPY $x10
4143
%1:_(s64) = G_ASSERT_ZEXT %0, 16
4244
%2:_(s16) = G_TRUNC %1(s64)
@@ -74,16 +76,16 @@ body: |
7476
; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
7577
; RV64I-NEXT: PseudoRET implicit $x10
7678
;
77-
; RV64ZBB-LABEL: name: bswap_i32
78-
; RV64ZBB: liveins: $x10
79-
; RV64ZBB-NEXT: {{ $}}
80-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
81-
; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
82-
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
83-
; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
84-
; RV64ZBB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
85-
; RV64ZBB-NEXT: $x10 = COPY [[LSHR]](s64)
86-
; RV64ZBB-NEXT: PseudoRET implicit $x10
79+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i32
80+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
81+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
82+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
83+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32
84+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[ASSERT_ZEXT]]
85+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
86+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[BSWAP]], [[C]](s64)
87+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[LSHR]](s64)
88+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
8789
%0:_(s64) = COPY $x10
8890
%1:_(s64) = G_ASSERT_ZEXT %0, 32
8991
%2:_(s32) = G_TRUNC %1(s64)
@@ -132,13 +134,13 @@ body: |
132134
; RV64I-NEXT: $x10 = COPY [[OR6]](s64)
133135
; RV64I-NEXT: PseudoRET implicit $x10
134136
;
135-
; RV64ZBB-LABEL: name: bswap_i64
136-
; RV64ZBB: liveins: $x10
137-
; RV64ZBB-NEXT: {{ $}}
138-
; RV64ZBB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
139-
; RV64ZBB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
140-
; RV64ZBB-NEXT: $x10 = COPY [[BSWAP]](s64)
141-
; RV64ZBB-NEXT: PseudoRET implicit $x10
137+
; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i64
138+
; RV64ZBB_OR_RV64ZBKB: liveins: $x10
139+
; RV64ZBB_OR_RV64ZBKB-NEXT: {{ $}}
140+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
141+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s64) = G_BSWAP [[COPY]]
142+
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[BSWAP]](s64)
143+
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
142144
%0:_(s64) = COPY $x10
143145
%1:_(s64) = G_BSWAP %0
144146
$x10 = COPY %1(s64)

0 commit comments

Comments
 (0)