|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals |
| 2 | +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor %s -o - | FileCheck %s |
| 3 | + |
| 4 | +@g1 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 5 | +@g2 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 6 | +@g3 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 7 | +@g4 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 8 | + |
| 9 | +;. |
| 10 | +; CHECK: @g1 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 11 | +; CHECK: @g2 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 12 | +; CHECK: @g3 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 13 | +; CHECK: @g4 = protected addrspace(1) externally_initialized global i32 0, align 4 |
| 14 | +;. |
| 15 | +define internal fastcc void @callee_infer(ptr addrspace(1) %x, i32 %y) { |
| 16 | +; CHECK-LABEL: define {{[^@]+}}@callee_infer |
| 17 | +; CHECK-SAME: (ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] { |
| 18 | +; CHECK-NEXT: entry: |
| 19 | +; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4 |
| 20 | +; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4 |
| 21 | +; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4 |
| 22 | +; CHECK-NEXT: ret void |
| 23 | +; |
| 24 | +entry: |
| 25 | + %x.val = load i32, ptr addrspace(1) %x, align 4 |
| 26 | + store i32 %x.val, ptr addrspace(1) @g3, align 4 |
| 27 | + store i32 %y, ptr addrspace(1) @g4, align 4 |
| 28 | + ret void |
| 29 | +} |
| 30 | + |
| 31 | +define amdgpu_kernel void @kernel_infer(ptr addrspace(1) %p1, ptr addrspace(1) %p2, i32 %x) { |
| 32 | +; CHECK-LABEL: define {{[^@]+}}@kernel_infer |
| 33 | +; CHECK-SAME: (ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]], i32 [[X:%.*]]) #[[ATTR0]] { |
| 34 | +; CHECK-NEXT: entry: |
| 35 | +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0 |
| 36 | +; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]] |
| 37 | +; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 [[X]]) |
| 38 | +; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 [[X]]) |
| 39 | +; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 1) |
| 40 | +; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 2) |
| 41 | +; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) [[P]], i32 [[X]]) |
| 42 | +; CHECK-NEXT: ret void |
| 43 | +; |
| 44 | +entry: |
| 45 | + %cmp = icmp sgt i32 %x, 0 |
| 46 | + %p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2 |
| 47 | + tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 %x) |
| 48 | + tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 %x) |
| 49 | + tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 1) |
| 50 | + tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 2) |
| 51 | + tail call fastcc void @callee_infer(ptr addrspace(1) %p, i32 %x) |
| 52 | + ret void |
| 53 | +} |
| 54 | + |
| 55 | +define amdgpu_kernel void @kernel_infer_indirect(ptr addrspace(1) %p1, ptr addrspace(1) %p2, i32 %x) { |
| 56 | +; CHECK-LABEL: define {{[^@]+}}@kernel_infer_indirect |
| 57 | +; CHECK-SAME: (ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]], i32 [[X:%.*]]) #[[ATTR1:[0-9]+]] { |
| 58 | +; CHECK-NEXT: entry: |
| 59 | +; CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8, addrspace(5) |
| 60 | +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0 |
| 61 | +; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]] |
| 62 | +; CHECK-NEXT: store ptr @kernel_infer, ptr addrspace(5) [[FN]], align 8 |
| 63 | +; CHECK-NEXT: [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr |
| 64 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g1, i32 [[X]]) |
| 65 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g2, i32 [[X]]) |
| 66 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g1, i32 1) |
| 67 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g2, i32 2) |
| 68 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[P]], i32 [[X]]) |
| 69 | +; CHECK-NEXT: ret void |
| 70 | +; |
| 71 | +entry: |
| 72 | + %fn = alloca ptr, addrspace(5) |
| 73 | + %cmp = icmp sgt i32 %x, 0 |
| 74 | + %p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2 |
| 75 | + store ptr @kernel_infer, ptr addrspace(5) %fn |
| 76 | + %fn.cast = addrspacecast ptr addrspace(5) %fn to ptr |
| 77 | + tail call fastcc void %fn.cast(ptr addrspace(1) @g1, i32 %x) |
| 78 | + tail call fastcc void %fn.cast(ptr addrspace(1) @g2, i32 %x) |
| 79 | + tail call fastcc void %fn.cast(ptr addrspace(1) @g1, i32 1) |
| 80 | + tail call fastcc void %fn.cast(ptr addrspace(1) @g2, i32 2) |
| 81 | + tail call fastcc void %fn.cast(ptr addrspace(1) %p, i32 %x) |
| 82 | + ret void |
| 83 | +} |
| 84 | + |
| 85 | +define internal fastcc void @callee_not_infer(ptr addrspace(1) %x, i32 %y) { |
| 86 | +; CHECK-LABEL: define {{[^@]+}}@callee_not_infer |
| 87 | +; CHECK-SAME: (ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] { |
| 88 | +; CHECK-NEXT: entry: |
| 89 | +; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4 |
| 90 | +; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4 |
| 91 | +; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4 |
| 92 | +; CHECK-NEXT: ret void |
| 93 | +; |
| 94 | +entry: |
| 95 | + %x.val = load i32, ptr addrspace(1) %x, align 4 |
| 96 | + store i32 %x.val, ptr addrspace(1) @g3, align 4 |
| 97 | + store i32 %y, ptr addrspace(1) @g4, align 4 |
| 98 | + ret void |
| 99 | +} |
| 100 | + |
| 101 | +define amdgpu_kernel void @kernel_not_infer(ptr addrspace(1) %q, ptr addrspace(1) %p1, ptr addrspace(1) %p2) { |
| 102 | +; CHECK-LABEL: define {{[^@]+}}@kernel_not_infer |
| 103 | +; CHECK-SAME: (ptr addrspace(1) [[Q:%.*]], ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]]) #[[ATTR0]] { |
| 104 | +; CHECK-NEXT: entry: |
| 105 | +; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() |
| 106 | +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[Q]], i32 [[ID_X]] |
| 107 | +; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4 |
| 108 | +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D]], 0 |
| 109 | +; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]] |
| 110 | +; CHECK-NEXT: tail call fastcc void @callee_not_infer(ptr addrspace(1) [[Q]], i32 [[ID_X]]) |
| 111 | +; CHECK-NEXT: tail call fastcc void @callee_not_infer(ptr addrspace(1) [[P]], i32 [[ID_X]]) |
| 112 | +; CHECK-NEXT: ret void |
| 113 | +; |
| 114 | +entry: |
| 115 | + %id.x = call i32 @llvm.amdgcn.workitem.id.x() |
| 116 | + %gep = getelementptr i32, ptr addrspace(1) %q, i32 %id.x |
| 117 | + %d = load i32, ptr addrspace(1) %gep |
| 118 | + %cmp = icmp sgt i32 %d, 0 |
| 119 | + %p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2 |
| 120 | + tail call fastcc void @callee_not_infer(ptr addrspace(1) %q, i32 %id.x) |
| 121 | + tail call fastcc void @callee_not_infer(ptr addrspace(1) %p, i32 %id.x) |
| 122 | + ret void |
| 123 | +} |
| 124 | + |
| 125 | +define amdgpu_kernel void @kernel_not_infer_indirect(ptr addrspace(1) %q, ptr addrspace(1) %p1, ptr addrspace(1) %p2) { |
| 126 | +; CHECK-LABEL: define {{[^@]+}}@kernel_not_infer_indirect |
| 127 | +; CHECK-SAME: (ptr addrspace(1) [[Q:%.*]], ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]]) #[[ATTR1]] { |
| 128 | +; CHECK-NEXT: entry: |
| 129 | +; CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8, addrspace(5) |
| 130 | +; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() |
| 131 | +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[Q]], i32 [[ID_X]] |
| 132 | +; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4 |
| 133 | +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D]], 0 |
| 134 | +; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]] |
| 135 | +; CHECK-NEXT: store ptr @kernel_not_infer, ptr addrspace(5) [[FN]], align 8 |
| 136 | +; CHECK-NEXT: [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr |
| 137 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[Q]], i32 [[ID_X]]) |
| 138 | +; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[P]], i32 [[ID_X]]) |
| 139 | +; CHECK-NEXT: ret void |
| 140 | +; |
| 141 | +entry: |
| 142 | + %fn = alloca ptr, addrspace(5) |
| 143 | + %id.x = call i32 @llvm.amdgcn.workitem.id.x() |
| 144 | + %gep = getelementptr i32, ptr addrspace(1) %q, i32 %id.x |
| 145 | + %d = load i32, ptr addrspace(1) %gep |
| 146 | + %cmp = icmp sgt i32 %d, 0 |
| 147 | + %p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2 |
| 148 | + store ptr @kernel_not_infer, ptr addrspace(5) %fn |
| 149 | + %fn.cast = addrspacecast ptr addrspace(5) %fn to ptr |
| 150 | + tail call fastcc void %fn.cast(ptr addrspace(1) %q, i32 %id.x) |
| 151 | + tail call fastcc void %fn.cast(ptr addrspace(1) %p, i32 %id.x) |
| 152 | + ret void |
| 153 | +} |
| 154 | +;. |
| 155 | +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" } |
| 156 | +; CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } |
| 157 | +; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } |
| 158 | +;. |
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