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[WIP][AMDGPU][Attributor] Infer inreg attribute in AMDGPUAttributor 
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5 files changed

+267
-4
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5 files changed

+267
-4
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
1212

1313
#include "llvm/CodeGen/MachinePassManager.h"
14+
#include "llvm/IR/CallingConv.h"
1415
#include "llvm/IR/PassManager.h"
1516
#include "llvm/Pass.h"
1617
#include "llvm/Support/AMDGPUAddrSpace.h"
@@ -501,6 +502,10 @@ static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
501502
return ASAliasRules[AS1][AS2];
502503
}
503504

505+
static inline bool isEntryPointCC(CallingConv::ID CC) {
506+
return CC == CallingConv::AMDGPU_KERNEL;
507+
}
508+
504509
}
505510

506511
} // End namespace llvm

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 101 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "GCNSubtarget.h"
1515
#include "Utils/AMDGPUBaseInfo.h"
1616
#include "llvm/Analysis/CycleAnalysis.h"
17+
#include "llvm/Analysis/UniformityAnalysis.h"
1718
#include "llvm/CodeGen/TargetPassConfig.h"
1819
#include "llvm/IR/IntrinsicsAMDGPU.h"
1920
#include "llvm/IR/IntrinsicsR600.h"
@@ -1014,6 +1015,99 @@ struct AAAMDGPUNoAGPR
10141015

10151016
const char AAAMDGPUNoAGPR::ID = 0;
10161017

1018+
struct AAAMDGPUInreg
1019+
: public IRAttribute<Attribute::InReg,
1020+
StateWrapper<BooleanState, AbstractAttribute>,
1021+
AAAMDGPUInreg> {
1022+
AAAMDGPUInreg(const IRPosition &IRP, Attributor &A) : IRAttribute(IRP) {}
1023+
1024+
/// Create an abstract attribute view for the position \p IRP.
1025+
static AAAMDGPUInreg &createForPosition(const IRPosition &IRP, Attributor &A);
1026+
1027+
/// See AbstractAttribute::getName()
1028+
const std::string getName() const override { return "AAAMDGPUInreg"; }
1029+
1030+
const std::string getAsStr(Attributor *A) const override {
1031+
return getAssumed() ? "inreg" : "non-inreg";
1032+
}
1033+
1034+
void trackStatistics() const override {}
1035+
1036+
/// See AbstractAttribute::getIdAddr()
1037+
const char *getIdAddr() const override { return &ID; }
1038+
1039+
/// This function should return true if the type of the \p AA is AAAMDGPUInreg
1040+
static bool classof(const AbstractAttribute *AA) {
1041+
return (AA->getIdAddr() == &ID);
1042+
}
1043+
1044+
/// Unique ID (due to the unique address)
1045+
static const char ID;
1046+
};
1047+
1048+
const char AAAMDGPUInreg::ID = 0;
1049+
1050+
namespace {
1051+
1052+
struct AAAMDGPUInregArgument : public AAAMDGPUInreg {
1053+
AAAMDGPUInregArgument(const IRPosition &IRP, Attributor &A)
1054+
: AAAMDGPUInreg(IRP, A) {}
1055+
1056+
void initialize(Attributor &A) override {
1057+
assert(!AMDGPU::isEntryPointCC(getAssociatedFunction()->getCallingConv()));
1058+
if (getAssociatedArgument()->hasAttribute(Attribute::InReg))
1059+
indicateOptimisticFixpoint();
1060+
}
1061+
1062+
ChangeStatus updateImpl(Attributor &A) override {
1063+
unsigned ArgNo = getAssociatedArgument()->getArgNo();
1064+
1065+
auto isUniform = [&](AbstractCallSite ACS) -> bool {
1066+
CallBase *CB = ACS.getInstruction();
1067+
Value *V = CB->getArgOperandUse(ArgNo);
1068+
if (isa<Constant>(V))
1069+
return true;
1070+
if (auto *I = dyn_cast<Instruction>(V)) {
1071+
auto *AU = A.getInfoCache()
1072+
.getAnalysisResultForFunction<UniformityInfoAnalysis>(
1073+
*I->getFunction());
1074+
return AU && AU->isUniform(I);
1075+
}
1076+
if (auto *Arg = dyn_cast<Argument>(V)) {
1077+
// We assume all entry point arguments are uniform.
1078+
if (AMDGPU::isEntryPointCC(Arg->getParent()->getCallingConv()))
1079+
return true;
1080+
auto *AA =
1081+
A.getOrCreateAAFor<AAAMDGPUInreg>(IRPosition::argument(*Arg));
1082+
return AA && AA->isValidState();
1083+
}
1084+
return false;
1085+
};
1086+
1087+
bool UsedAssumedInformation = false;
1088+
if (!A.checkForAllCallSites(isUniform, *this, /*RequireAllCallSites=*/true,
1089+
UsedAssumedInformation))
1090+
return indicatePessimisticFixpoint();
1091+
1092+
if (!UsedAssumedInformation)
1093+
return indicateOptimisticFixpoint();
1094+
1095+
return ChangeStatus::UNCHANGED;
1096+
}
1097+
};
1098+
1099+
} // namespace
1100+
1101+
AAAMDGPUInreg &AAAMDGPUInreg::createForPosition(const IRPosition &IRP,
1102+
Attributor &A) {
1103+
switch (IRP.getPositionKind()) {
1104+
case IRPosition::IRP_ARGUMENT:
1105+
return *new (A.Allocator) AAAMDGPUInregArgument(IRP, A);
1106+
default:
1107+
llvm_unreachable("not a valid position for AAAMDGPUInreg");
1108+
}
1109+
}
1110+
10171111
static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
10181112
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
10191113
for (unsigned I = 0;
@@ -1046,7 +1140,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
10461140
&AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID, &AACallEdges::ID,
10471141
&AAPointerInfo::ID, &AAPotentialConstantValues::ID,
10481142
&AAUnderlyingObjects::ID, &AAAddressSpace::ID, &AAIndirectCallInfo::ID,
1049-
&AAInstanceInfo::ID});
1143+
&AAInstanceInfo::ID, &AAAMDGPUInreg::ID});
10501144

10511145
AttributorConfig AC(CGUpdater);
10521146
AC.IsClosedWorldModule = Options.IsClosedWorld;
@@ -1090,6 +1184,11 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
10901184
IRPosition::value(*SI->getPointerOperand()));
10911185
}
10921186
}
1187+
1188+
if (!AMDGPU::isEntryPointCC(F.getCallingConv())) {
1189+
for (auto &Arg : F.args())
1190+
A.getOrCreateAAFor<AAAMDGPUInreg>(IRPosition::argument(Arg));
1191+
}
10931192
}
10941193

10951194
ChangeStatus Change = A.run();
@@ -1118,6 +1217,7 @@ class AMDGPUAttributorLegacy : public ModulePass {
11181217

11191218
void getAnalysisUsage(AnalysisUsage &AU) const override {
11201219
AU.addRequired<CycleInfoWrapperPass>();
1220+
AU.addRequired<UniformityInfoWrapperPass>();
11211221
}
11221222

11231223
StringRef getPassName() const override { return "AMDGPU Attributor"; }

‎llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88

99
define internal fastcc void @foo(ptr %kg) {
1010
; CHECK-LABEL: define internal fastcc void @foo(
11-
; CHECK-SAME: ptr [[KG:%.*]]) #[[ATTR0:[0-9]+]] {
11+
; CHECK-SAME: ptr inreg [[KG:%.*]]) #[[ATTR0:[0-9]+]] {
1212
; CHECK-NEXT: [[ENTRY:.*:]]
1313
; CHECK-NEXT: [[CLOSURE_I25_I:%.*]] = getelementptr i8, ptr [[KG]], i64 336
1414
; CHECK-NEXT: [[NUM_CLOSURE_I26_I:%.*]] = getelementptr i8, ptr [[KG]], i64 276

‎llvm/test/CodeGen/AMDGPU/inreg-inference.ll

Lines changed: 158 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,158 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
2+
; RUN: opt -S -mtriple=amdgcn-unknown-unknown -passes=amdgpu-attributor %s -o - | FileCheck %s
3+
4+
@g1 = protected addrspace(1) externally_initialized global i32 0, align 4
5+
@g2 = protected addrspace(1) externally_initialized global i32 0, align 4
6+
@g3 = protected addrspace(1) externally_initialized global i32 0, align 4
7+
@g4 = protected addrspace(1) externally_initialized global i32 0, align 4
8+
9+
;.
10+
; CHECK: @g1 = protected addrspace(1) externally_initialized global i32 0, align 4
11+
; CHECK: @g2 = protected addrspace(1) externally_initialized global i32 0, align 4
12+
; CHECK: @g3 = protected addrspace(1) externally_initialized global i32 0, align 4
13+
; CHECK: @g4 = protected addrspace(1) externally_initialized global i32 0, align 4
14+
;.
15+
define internal fastcc void @callee_infer(ptr addrspace(1) %x, i32 %y) {
16+
; CHECK-LABEL: define {{[^@]+}}@callee_infer
17+
; CHECK-SAME: (ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
18+
; CHECK-NEXT: entry:
19+
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
20+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
21+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
22+
; CHECK-NEXT: ret void
23+
;
24+
entry:
25+
%x.val = load i32, ptr addrspace(1) %x, align 4
26+
store i32 %x.val, ptr addrspace(1) @g3, align 4
27+
store i32 %y, ptr addrspace(1) @g4, align 4
28+
ret void
29+
}
30+
31+
define amdgpu_kernel void @kernel_infer(ptr addrspace(1) %p1, ptr addrspace(1) %p2, i32 %x) {
32+
; CHECK-LABEL: define {{[^@]+}}@kernel_infer
33+
; CHECK-SAME: (ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]], i32 [[X:%.*]]) #[[ATTR0]] {
34+
; CHECK-NEXT: entry:
35+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0
36+
; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]]
37+
; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 [[X]])
38+
; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 [[X]])
39+
; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 1)
40+
; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 2)
41+
; CHECK-NEXT: tail call fastcc void @callee_infer(ptr addrspace(1) [[P]], i32 [[X]])
42+
; CHECK-NEXT: ret void
43+
;
44+
entry:
45+
%cmp = icmp sgt i32 %x, 0
46+
%p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2
47+
tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 %x)
48+
tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 %x)
49+
tail call fastcc void @callee_infer(ptr addrspace(1) @g1, i32 1)
50+
tail call fastcc void @callee_infer(ptr addrspace(1) @g2, i32 2)
51+
tail call fastcc void @callee_infer(ptr addrspace(1) %p, i32 %x)
52+
ret void
53+
}
54+
55+
define amdgpu_kernel void @kernel_infer_indirect(ptr addrspace(1) %p1, ptr addrspace(1) %p2, i32 %x) {
56+
; CHECK-LABEL: define {{[^@]+}}@kernel_infer_indirect
57+
; CHECK-SAME: (ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]], i32 [[X:%.*]]) #[[ATTR1:[0-9]+]] {
58+
; CHECK-NEXT: entry:
59+
; CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8, addrspace(5)
60+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], 0
61+
; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]]
62+
; CHECK-NEXT: store ptr @kernel_infer, ptr addrspace(5) [[FN]], align 8
63+
; CHECK-NEXT: [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr
64+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g1, i32 [[X]])
65+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g2, i32 [[X]])
66+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g1, i32 1)
67+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) @g2, i32 2)
68+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[P]], i32 [[X]])
69+
; CHECK-NEXT: ret void
70+
;
71+
entry:
72+
%fn = alloca ptr, addrspace(5)
73+
%cmp = icmp sgt i32 %x, 0
74+
%p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2
75+
store ptr @kernel_infer, ptr addrspace(5) %fn
76+
%fn.cast = addrspacecast ptr addrspace(5) %fn to ptr
77+
tail call fastcc void %fn.cast(ptr addrspace(1) @g1, i32 %x)
78+
tail call fastcc void %fn.cast(ptr addrspace(1) @g2, i32 %x)
79+
tail call fastcc void %fn.cast(ptr addrspace(1) @g1, i32 1)
80+
tail call fastcc void %fn.cast(ptr addrspace(1) @g2, i32 2)
81+
tail call fastcc void %fn.cast(ptr addrspace(1) %p, i32 %x)
82+
ret void
83+
}
84+
85+
define internal fastcc void @callee_not_infer(ptr addrspace(1) %x, i32 %y) {
86+
; CHECK-LABEL: define {{[^@]+}}@callee_not_infer
87+
; CHECK-SAME: (ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
88+
; CHECK-NEXT: entry:
89+
; CHECK-NEXT: [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
90+
; CHECK-NEXT: store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
91+
; CHECK-NEXT: store i32 [[Y]], ptr addrspace(1) @g4, align 4
92+
; CHECK-NEXT: ret void
93+
;
94+
entry:
95+
%x.val = load i32, ptr addrspace(1) %x, align 4
96+
store i32 %x.val, ptr addrspace(1) @g3, align 4
97+
store i32 %y, ptr addrspace(1) @g4, align 4
98+
ret void
99+
}
100+
101+
define amdgpu_kernel void @kernel_not_infer(ptr addrspace(1) %q, ptr addrspace(1) %p1, ptr addrspace(1) %p2) {
102+
; CHECK-LABEL: define {{[^@]+}}@kernel_not_infer
103+
; CHECK-SAME: (ptr addrspace(1) [[Q:%.*]], ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]]) #[[ATTR0]] {
104+
; CHECK-NEXT: entry:
105+
; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
106+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[Q]], i32 [[ID_X]]
107+
; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4
108+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D]], 0
109+
; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]]
110+
; CHECK-NEXT: tail call fastcc void @callee_not_infer(ptr addrspace(1) [[Q]], i32 [[ID_X]])
111+
; CHECK-NEXT: tail call fastcc void @callee_not_infer(ptr addrspace(1) [[P]], i32 [[ID_X]])
112+
; CHECK-NEXT: ret void
113+
;
114+
entry:
115+
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
116+
%gep = getelementptr i32, ptr addrspace(1) %q, i32 %id.x
117+
%d = load i32, ptr addrspace(1) %gep
118+
%cmp = icmp sgt i32 %d, 0
119+
%p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2
120+
tail call fastcc void @callee_not_infer(ptr addrspace(1) %q, i32 %id.x)
121+
tail call fastcc void @callee_not_infer(ptr addrspace(1) %p, i32 %id.x)
122+
ret void
123+
}
124+
125+
define amdgpu_kernel void @kernel_not_infer_indirect(ptr addrspace(1) %q, ptr addrspace(1) %p1, ptr addrspace(1) %p2) {
126+
; CHECK-LABEL: define {{[^@]+}}@kernel_not_infer_indirect
127+
; CHECK-SAME: (ptr addrspace(1) [[Q:%.*]], ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]]) #[[ATTR1]] {
128+
; CHECK-NEXT: entry:
129+
; CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8, addrspace(5)
130+
; CHECK-NEXT: [[ID_X:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
131+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[Q]], i32 [[ID_X]]
132+
; CHECK-NEXT: [[D:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4
133+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D]], 0
134+
; CHECK-NEXT: [[P:%.*]] = select i1 [[CMP]], ptr addrspace(1) [[P1]], ptr addrspace(1) [[P2]]
135+
; CHECK-NEXT: store ptr @kernel_not_infer, ptr addrspace(5) [[FN]], align 8
136+
; CHECK-NEXT: [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr
137+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[Q]], i32 [[ID_X]])
138+
; CHECK-NEXT: tail call fastcc void [[FN_CAST]](ptr addrspace(1) [[P]], i32 [[ID_X]])
139+
; CHECK-NEXT: ret void
140+
;
141+
entry:
142+
%fn = alloca ptr, addrspace(5)
143+
%id.x = call i32 @llvm.amdgcn.workitem.id.x()
144+
%gep = getelementptr i32, ptr addrspace(1) %q, i32 %id.x
145+
%d = load i32, ptr addrspace(1) %gep
146+
%cmp = icmp sgt i32 %d, 0
147+
%p = select i1 %cmp, ptr addrspace(1) %p1, ptr addrspace(1) %p2
148+
store ptr @kernel_not_infer, ptr addrspace(5) %fn
149+
%fn.cast = addrspacecast ptr addrspace(5) %fn to ptr
150+
tail call fastcc void %fn.cast(ptr addrspace(1) %q, i32 %id.x)
151+
tail call fastcc void %fn.cast(ptr addrspace(1) %p, i32 %id.x)
152+
ret void
153+
}
154+
;.
155+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
156+
; CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
157+
; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
158+
;.

‎llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ define amdgpu_kernel void @kernel_lds() {
148148

149149
define internal i16 @mutual_recursion_0(i16 %arg) {
150150
; CHECK-LABEL: define internal i16 @mutual_recursion_0(
151-
; CHECK-SAME: i16 [[ARG:%.*]]) #[[ATTR0]] {
151+
; CHECK-SAME: i16 inreg [[ARG:%.*]]) #[[ATTR0]] {
152152
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
153153
; CHECK-NEXT: [[RECURSIVE_KERNEL_LDS:%.*]] = getelementptr inbounds [3 x [2 x i32]], ptr addrspace(4) @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
154154
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(4) [[RECURSIVE_KERNEL_LDS]], align 4
@@ -168,7 +168,7 @@ define internal i16 @mutual_recursion_0(i16 %arg) {
168168

169169
define internal void @mutual_recursion_1(i16 %arg) {
170170
; CHECK-LABEL: define internal void @mutual_recursion_1(
171-
; CHECK-SAME: i16 [[ARG:%.*]]) #[[ATTR0]] {
171+
; CHECK-SAME: i16 inreg [[ARG:%.*]]) #[[ATTR0]] {
172172
; CHECK-NEXT: call void @mutual_recursion_0(i16 [[ARG]])
173173
; CHECK-NEXT: ret void
174174
;

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