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1 parent 296dee6 commit b48d918Copy full SHA for b48d918
llvm/test/CodeGen/RISCV/rvv/vlopt-same-vl.ll
@@ -3,6 +3,13 @@
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; REQUIRES: asserts
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+; GitHub Issue #123862 provided a case where the riscv-vl-optimizer pass was
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+; very slow. It was found that that case benefited greatly from aborting due
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+; to CommonVL == VLOp. Adding the case provided in the issue would show up
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+; as a long running test instead of a test failure. We would likley have a hard
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+; time figuring if that case had a regression. So instead, we check this output
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+; which was responsible for speeding it up.
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+
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define <vscale x 4 x i32> @same_vl_imm(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK: User VL is: 4
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; CHECK-NEXT: Abort due to CommonVL == VLOp, no point in reducing.
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