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remove LoongArchISD:{DIV_W,MOD_W} , add div32 support in sys::getHostCPUFeatures & update tests
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7 files changed

+45
-56
lines changed

7 files changed

+45
-56
lines changed

‎llvm/lib/Target/LoongArch/LoongArch.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">;
126126
// Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended.
127127
def FeatureDiv32
128128
: SubtargetFeature<"div32", "HasDiv32", "true",
129-
"Support div.w[u] and mod.w[u] can handle inputs that are not sign-extended">;
129+
"Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended">;
130130
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">;
131131

132132
def TunePreferWInst

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -141,8 +141,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
141141

142142
setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
143143
setOperationAction(ISD::BSWAP, MVT::i32, Custom);
144-
setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32,
145-
Custom);
144+
setOperationAction({ISD::UDIV, ISD::UREM}, MVT::i32, Custom);
146145
setOperationAction(ISD::LROUND, MVT::i32, Custom);
147146
}
148147

@@ -2632,12 +2631,8 @@ static LoongArchISD::NodeType getLoongArchWOpcode(unsigned Opcode) {
26322631
switch (Opcode) {
26332632
default:
26342633
llvm_unreachable("Unexpected opcode");
2635-
case ISD::SDIV:
2636-
return LoongArchISD::DIV_W;
26372634
case ISD::UDIV:
26382635
return LoongArchISD::DIV_WU;
2639-
case ISD::SREM:
2640-
return LoongArchISD::MOD_W;
26412636
case ISD::UREM:
26422637
return LoongArchISD::MOD_WU;
26432638
case ISD::SHL:
@@ -2834,9 +2829,7 @@ void LoongArchTargetLowering::ReplaceNodeResults(
28342829
"Unexpected custom legalisation");
28352830
Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
28362831
break;
2837-
case ISD::SDIV:
28382832
case ISD::UDIV:
2839-
case ISD::SREM:
28402833
case ISD::UREM:
28412834
assert(VT == MVT::i32 && Subtarget.is64Bit() &&
28422835
"Unexpected custom legalisation");
@@ -4679,9 +4672,7 @@ const char *LoongArchTargetLowering::getTargetNodeName(unsigned Opcode) const {
46794672
NODE_NAME_CASE(BITREV_W)
46804673
NODE_NAME_CASE(ROTR_W)
46814674
NODE_NAME_CASE(ROTL_W)
4682-
NODE_NAME_CASE(DIV_W)
46834675
NODE_NAME_CASE(DIV_WU)
4684-
NODE_NAME_CASE(MOD_W)
46854676
NODE_NAME_CASE(MOD_WU)
46864677
NODE_NAME_CASE(CLZ_W)
46874678
NODE_NAME_CASE(CTZ_W)

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,6 @@ enum NodeType : unsigned {
4444
ROTR_W,
4545

4646
// unsigned 32-bit integer division
47-
DIV_W,
48-
MOD_W,
4947
DIV_WU,
5048
MOD_WU,
5149

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.td

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,9 +85,7 @@ def loongarch_sll_w : SDNode<"LoongArchISD::SLL_W", SDT_LoongArchIntBinOpW>;
8585
def loongarch_sra_w : SDNode<"LoongArchISD::SRA_W", SDT_LoongArchIntBinOpW>;
8686
def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
8787
def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
88-
def loongarch_div_w : SDNode<"LoongArchISD::DIV_W", SDT_LoongArchIntBinOpW>;
8988
def loongarch_div_wu : SDNode<"LoongArchISD::DIV_WU", SDT_LoongArchIntBinOpW>;
90-
def loongarch_mod_w : SDNode<"LoongArchISD::MOD_W", SDT_LoongArchIntBinOpW>;
9189
def loongarch_mod_wu : SDNode<"LoongArchISD::MOD_WU", SDT_LoongArchIntBinOpW>;
9290
def loongarch_crc_w_b_w
9391
: SDNode<"LoongArchISD::CRC_W_B_W", SDT_LoongArchIntBinOpW, [SDNPHasChain]>;
@@ -1158,12 +1156,10 @@ def : PatGprGpr<sub, SUB_D>;
11581156
def : PatGprGpr<sdiv, DIV_D>;
11591157
def : PatGprGpr_32<sdiv, DIV_W>;
11601158
def : PatGprGpr<udiv, DIV_DU>;
1161-
def : PatGprGpr<loongarch_div_w, DIV_W>;
11621159
def : PatGprGpr<loongarch_div_wu, DIV_WU>;
11631160
def : PatGprGpr<srem, MOD_D>;
11641161
def : PatGprGpr_32<srem, MOD_W>;
11651162
def : PatGprGpr<urem, MOD_DU>;
1166-
def : PatGprGpr<loongarch_mod_w, MOD_W>;
11671163
def : PatGprGpr<loongarch_mod_wu, MOD_WU>;
11681164
def : PatGprGpr<shiftop<rotr>, ROTR_D>;
11691165
def : PatGprGpr<shiftopw<loongarch_rotr_w>, ROTR_W>;

‎llvm/lib/TargetParser/Host.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2025,12 +2025,12 @@ const StringMap<bool> sys::getHostCPUFeatures() {
20252025
Features["lvz"] = hwcap & (1UL << 9); // HWCAP_LOONGARCH_LVZ
20262026

20272027
Features["frecipe"] = cpucfg2 & (1U << 25); // CPUCFG.2.FRECIPE
2028+
Features["div32"] = cpucfg2 & (1U << 26); // CPUCFG.2.DIV32
20282029
Features["lam-bh"] = cpucfg2 & (1U << 27); // CPUCFG.2.LAM_BH
20292030

20302031
Features["ld-seq-sa"] = cpucfg3 & (1U << 23); // CPUCFG.3.LD_SEQ_SA
20312032

20322033
// TODO: Need to complete.
2033-
// Features["div32"] = cpucfg2 & (1U << 26); // CPUCFG.2.DIV32
20342034
// Features["lamcas"] = cpucfg2 & (1U << 28); // CPUCFG.2.LAMCAS
20352035
// Features["llacq-screl"] = cpucfg2 & (1U << 29); // CPUCFG.2.LLACQ_SCREL
20362036
// Features["scq"] = cpucfg2 & (1U << 30); // CPUCFG.2.SCQ

‎llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll

Lines changed: 30 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2,25 +2,27 @@
22
; RUN: llc --mtriple=loongarch64 -mattr=+d,-div32 < %s | FileCheck %s --check-prefix=LA64
33
; RUN: llc --mtriple=loongarch64 -mattr=+d,+div32 < %s | FileCheck %s --check-prefix=LA64-DIV32
44

5-
define i32 @divw(i64 %0, i64 %1) {
5+
define i32 @divw(i64 %a, i64 %b) {
66
; LA64-LABEL: divw:
77
; LA64: # %bb.0:
8-
; LA64-NEXT: addi.w $a1, $a1, 0
98
; LA64-NEXT: addi.w $a0, $a0, 0
10-
; LA64-NEXT: div.w $a0, $a0, $a1
9+
; LA64-NEXT: addi.w $a1, $a1, 0
10+
; LA64-NEXT: div.d $a0, $a0, $a1
1111
; LA64-NEXT: ret
1212
;
1313
; LA64-DIV32-LABEL: divw:
1414
; LA64-DIV32: # %bb.0:
15-
; LA64-DIV32-NEXT: div.w $a0, $a0, $a1
15+
; LA64-DIV32-NEXT: addi.w $a0, $a0, 0
16+
; LA64-DIV32-NEXT: addi.w $a1, $a1, 0
17+
; LA64-DIV32-NEXT: div.d $a0, $a0, $a1
1618
; LA64-DIV32-NEXT: ret
17-
%3 = trunc i64 %0 to i32
18-
%4 = trunc i64 %1 to i32
19-
%5 = sdiv i32 %3, %4
20-
ret i32 %5
19+
%conv1 = trunc i64 %a to i32
20+
%conv2 = trunc i64 %b to i32
21+
%r = sdiv i32 %conv1, %conv2
22+
ret i32 %r
2123
}
2224

23-
define i32 @divwu(i64 %0, i64 %1) {
25+
define i32 @divwu(i64 %a, i64 %b) {
2426
; LA64-LABEL: divwu:
2527
; LA64: # %bb.0:
2628
; LA64-NEXT: addi.w $a1, $a1, 0
@@ -32,31 +34,33 @@ define i32 @divwu(i64 %0, i64 %1) {
3234
; LA64-DIV32: # %bb.0:
3335
; LA64-DIV32-NEXT: div.wu $a0, $a0, $a1
3436
; LA64-DIV32-NEXT: ret
35-
%3 = trunc i64 %0 to i32
36-
%4 = trunc i64 %1 to i32
37-
%5 = udiv i32 %3, %4
38-
ret i32 %5
37+
%conv1 = trunc i64 %a to i32
38+
%conv2 = trunc i64 %b to i32
39+
%r = udiv i32 %conv1, %conv2
40+
ret i32 %r
3941
}
4042

41-
define i32 @modw(i64 %0, i64 %1) {
43+
define i32 @modw(i64 %a, i64 %b) {
4244
; LA64-LABEL: modw:
4345
; LA64: # %bb.0:
44-
; LA64-NEXT: addi.w $a1, $a1, 0
4546
; LA64-NEXT: addi.w $a0, $a0, 0
46-
; LA64-NEXT: mod.w $a0, $a0, $a1
47+
; LA64-NEXT: addi.w $a1, $a1, 0
48+
; LA64-NEXT: mod.d $a0, $a0, $a1
4749
; LA64-NEXT: ret
4850
;
4951
; LA64-DIV32-LABEL: modw:
5052
; LA64-DIV32: # %bb.0:
51-
; LA64-DIV32-NEXT: mod.w $a0, $a0, $a1
53+
; LA64-DIV32-NEXT: addi.w $a0, $a0, 0
54+
; LA64-DIV32-NEXT: addi.w $a1, $a1, 0
55+
; LA64-DIV32-NEXT: mod.d $a0, $a0, $a1
5256
; LA64-DIV32-NEXT: ret
53-
%3 = trunc i64 %0 to i32
54-
%4 = trunc i64 %1 to i32
55-
%5 = srem i32 %3, %4
56-
ret i32 %5
57+
%conv1 = trunc i64 %a to i32
58+
%conv2 = trunc i64 %b to i32
59+
%r = srem i32 %conv1, %conv2
60+
ret i32 %r
5761
}
5862

59-
define i32 @modwu(i64 %0, i64 %1) {
63+
define i32 @modwu(i64 %a, i64 %b) {
6064
; LA64-LABEL: modwu:
6165
; LA64: # %bb.0:
6266
; LA64-NEXT: addi.w $a1, $a1, 0
@@ -68,8 +72,8 @@ define i32 @modwu(i64 %0, i64 %1) {
6872
; LA64-DIV32: # %bb.0:
6973
; LA64-DIV32-NEXT: mod.wu $a0, $a0, $a1
7074
; LA64-DIV32-NEXT: ret
71-
%3 = trunc i64 %0 to i32
72-
%4 = trunc i64 %1 to i32
73-
%5 = urem i32 %3, %4
74-
ret i32 %5
75+
%conv1 = trunc i64 %a to i32
76+
%conv2 = trunc i64 %b to i32
77+
%r = urem i32 %conv1, %conv2
78+
ret i32 %r
7579
}

‎llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
121121
; LA64: # %bb.0: # %entry
122122
; LA64-NEXT: addi.w $a1, $a1, 0
123123
; LA64-NEXT: addi.w $a0, $a0, 0
124-
; LA64-NEXT: div.w $a0, $a0, $a1
124+
; LA64-NEXT: div.d $a0, $a0, $a1
125125
; LA64-NEXT: ret
126126
;
127127
; LA32-TRAP-LABEL: sdiv_i32:
@@ -137,7 +137,7 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
137137
; LA64-TRAP: # %bb.0: # %entry
138138
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
139139
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
140-
; LA64-TRAP-NEXT: div.w $a0, $a0, $a1
140+
; LA64-TRAP-NEXT: div.d $a0, $a0, $a1
141141
; LA64-TRAP-NEXT: bnez $a1, .LBB3_2
142142
; LA64-TRAP-NEXT: # %bb.1: # %entry
143143
; LA64-TRAP-NEXT: break 7
@@ -156,7 +156,7 @@ define i32 @sdiv_ui32_si32_si32(i32 signext %a, i32 signext %b) {
156156
;
157157
; LA64-LABEL: sdiv_ui32_si32_si32:
158158
; LA64: # %bb.0: # %entry
159-
; LA64-NEXT: div.w $a0, $a0, $a1
159+
; LA64-NEXT: div.d $a0, $a0, $a1
160160
; LA64-NEXT: ret
161161
;
162162
; LA32-TRAP-LABEL: sdiv_ui32_si32_si32:
@@ -170,7 +170,7 @@ define i32 @sdiv_ui32_si32_si32(i32 signext %a, i32 signext %b) {
170170
;
171171
; LA64-TRAP-LABEL: sdiv_ui32_si32_si32:
172172
; LA64-TRAP: # %bb.0: # %entry
173-
; LA64-TRAP-NEXT: div.w $a0, $a0, $a1
173+
; LA64-TRAP-NEXT: div.d $a0, $a0, $a1
174174
; LA64-TRAP-NEXT: bnez $a1, .LBB4_2
175175
; LA64-TRAP-NEXT: # %bb.1: # %entry
176176
; LA64-TRAP-NEXT: break 7
@@ -693,7 +693,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
693693
; LA64: # %bb.0: # %entry
694694
; LA64-NEXT: addi.w $a1, $a1, 0
695695
; LA64-NEXT: addi.w $a0, $a0, 0
696-
; LA64-NEXT: mod.w $a0, $a0, $a1
696+
; LA64-NEXT: mod.d $a0, $a0, $a1
697697
; LA64-NEXT: ret
698698
;
699699
; LA32-TRAP-LABEL: srem_i32:
@@ -709,7 +709,7 @@ define i32 @srem_i32(i32 %a, i32 %b) {
709709
; LA64-TRAP: # %bb.0: # %entry
710710
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
711711
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
712-
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
712+
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
713713
; LA64-TRAP-NEXT: bnez $a1, .LBB19_2
714714
; LA64-TRAP-NEXT: # %bb.1: # %entry
715715
; LA64-TRAP-NEXT: break 7
@@ -728,7 +728,7 @@ define i32 @srem_ui32_si32_si32(i32 signext %a, i32 signext %b) {
728728
;
729729
; LA64-LABEL: srem_ui32_si32_si32:
730730
; LA64: # %bb.0: # %entry
731-
; LA64-NEXT: mod.w $a0, $a0, $a1
731+
; LA64-NEXT: mod.d $a0, $a0, $a1
732732
; LA64-NEXT: ret
733733
;
734734
; LA32-TRAP-LABEL: srem_ui32_si32_si32:
@@ -742,7 +742,7 @@ define i32 @srem_ui32_si32_si32(i32 signext %a, i32 signext %b) {
742742
;
743743
; LA64-TRAP-LABEL: srem_ui32_si32_si32:
744744
; LA64-TRAP: # %bb.0: # %entry
745-
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
745+
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
746746
; LA64-TRAP-NEXT: bnez $a1, .LBB20_2
747747
; LA64-TRAP-NEXT: # %bb.1: # %entry
748748
; LA64-TRAP-NEXT: break 7
@@ -763,7 +763,7 @@ define signext i32 @srem_si32_ui32_ui32(i32 %a, i32 %b) {
763763
; LA64: # %bb.0: # %entry
764764
; LA64-NEXT: addi.w $a1, $a1, 0
765765
; LA64-NEXT: addi.w $a0, $a0, 0
766-
; LA64-NEXT: mod.w $a0, $a0, $a1
766+
; LA64-NEXT: mod.d $a0, $a0, $a1
767767
; LA64-NEXT: ret
768768
;
769769
; LA32-TRAP-LABEL: srem_si32_ui32_ui32:
@@ -779,7 +779,7 @@ define signext i32 @srem_si32_ui32_ui32(i32 %a, i32 %b) {
779779
; LA64-TRAP: # %bb.0: # %entry
780780
; LA64-TRAP-NEXT: addi.w $a1, $a1, 0
781781
; LA64-TRAP-NEXT: addi.w $a0, $a0, 0
782-
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
782+
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
783783
; LA64-TRAP-NEXT: bnez $a1, .LBB21_2
784784
; LA64-TRAP-NEXT: # %bb.1: # %entry
785785
; LA64-TRAP-NEXT: break 7
@@ -798,7 +798,7 @@ define signext i32 @srem_si32_si32_si32(i32 signext %a, i32 signext %b) {
798798
;
799799
; LA64-LABEL: srem_si32_si32_si32:
800800
; LA64: # %bb.0: # %entry
801-
; LA64-NEXT: mod.w $a0, $a0, $a1
801+
; LA64-NEXT: mod.d $a0, $a0, $a1
802802
; LA64-NEXT: ret
803803
;
804804
; LA32-TRAP-LABEL: srem_si32_si32_si32:
@@ -812,7 +812,7 @@ define signext i32 @srem_si32_si32_si32(i32 signext %a, i32 signext %b) {
812812
;
813813
; LA64-TRAP-LABEL: srem_si32_si32_si32:
814814
; LA64-TRAP: # %bb.0: # %entry
815-
; LA64-TRAP-NEXT: mod.w $a0, $a0, $a1
815+
; LA64-TRAP-NEXT: mod.d $a0, $a0, $a1
816816
; LA64-TRAP-NEXT: bnez $a1, .LBB22_2
817817
; LA64-TRAP-NEXT: # %bb.1: # %entry
818818
; LA64-TRAP-NEXT: break 7

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