@@ -2617,20 +2617,19 @@ defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp>, E
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multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
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string OpcodeStr, RegisterClass KRC, ValueType vvt,
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X86MemOperand x86memop, string Suffix = ""> {
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- let explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in {
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- let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
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- def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
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- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
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- Sched<[WriteMove]>;
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- def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
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- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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- [(set KRC:$dst, (vvt (load addr:$src)))]>,
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- Sched<[WriteLoad]>, NoCD8;
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- def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
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- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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- [(store KRC:$src, addr:$dst)]>,
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- Sched<[WriteStore]>, NoCD8;
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- }
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+ let isMoveReg = 1, hasSideEffects = 0, SchedRW = [WriteMove],
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+ explicitOpPrefix = !if(!eq(Suffix, ""), NoExplicitOpPrefix, ExplicitEVEX) in
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+ def kk#Suffix : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
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+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
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+ Sched<[WriteMove]>;
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+ def km#Suffix : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
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+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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+ [(set KRC:$dst, (vvt (load addr:$src)))]>,
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+ Sched<[WriteLoad]>, NoCD8;
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+ def mk#Suffix : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
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+ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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+ [(store KRC:$src, addr:$dst)]>,
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+ Sched<[WriteStore]>, NoCD8;
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}
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multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
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