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sylvestresylvestre
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Revert "[Xtensa] Implement Windowed Register Option. (#121118)"
This reverts commit 0dcb16e.
1 parent 6e1ea7e commit 8662bd6

18 files changed

+9
-546
lines changed

‎llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp

Lines changed: 1 addition & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
1212
#include "MCTargetDesc/XtensaMCTargetDesc.h"
1313
#include "MCTargetDesc/XtensaTargetStreamer.h"
1414
#include "TargetInfo/XtensaTargetInfo.h"
15-
#include "XtensaUtils.h"
1615
#include "llvm/ADT/STLExtras.h"
1716
#include "llvm/ADT/StringSwitch.h"
1817
#include "llvm/MC/MCContext.h"
@@ -74,7 +73,6 @@ class XtensaAsmParser : public MCTargetAsmParser {
7473
SMLoc &EndLoc) override {
7574
return ParseStatus::NoMatch;
7675
}
77-
7876
ParseStatus parsePCRelTarget(OperandVector &Operands);
7977
bool parseLiteralDirective(SMLoc L);
8078

@@ -91,10 +89,6 @@ class XtensaAsmParser : public MCTargetAsmParser {
9189
: MCTargetAsmParser(Options, STI, MII) {
9290
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9391
}
94-
95-
bool hasWindowed() const {
96-
return getSTI().getFeatureBits()[Xtensa::FeatureWindowed];
97-
};
9892
};
9993

10094
// Return true if Expr is in the range [MinValue, MaxValue].
@@ -187,11 +181,6 @@ struct XtensaOperand : public MCParsedAsmOperand {
187181
((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
188182
}
189183

190-
bool isentry_imm12() const {
191-
return isImm(0, 32760) &&
192-
((cast<MCConstantExpr>(getImm())->getValue() % 8) == 0);
193-
}
194-
195184
bool isUimm4() const { return isImm(0, 15); }
196185

197186
bool isUimm5() const { return isImm(0, 31); }
@@ -209,11 +198,6 @@ struct XtensaOperand : public MCParsedAsmOperand {
209198

210199
bool isImm32n_95() const { return isImm(-32, 95); }
211200

212-
bool isImm64n_4n() const {
213-
return isImm(-64, -4) &&
214-
((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
215-
}
216-
217201
bool isB4const() const {
218202
if (Kind != Immediate)
219203
return false;
@@ -507,12 +491,6 @@ bool XtensaAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
507491
case Match_InvalidImm32n_95:
508492
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
509493
"expected immediate in range [-32, 95]");
510-
case Match_InvalidImm64n_4n:
511-
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
512-
"expected immediate in range [-64, -4]");
513-
case Match_InvalidImm8n_7:
514-
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
515-
"expected immediate in range [-8, 7]");
516494
case Match_InvalidShimm1_31:
517495
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
518496
"expected immediate in range [1, 31]");
@@ -537,10 +515,6 @@ bool XtensaAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
537515
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
538516
"expected immediate in range [0, 60], first 2 bits "
539517
"should be zero");
540-
case Match_Invalidentry_imm12:
541-
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
542-
"expected immediate in range [0, 32760], first 3 bits "
543-
"should be zero");
544518
}
545519

546520
report_fatal_error("Unknown match type detected!");
@@ -627,10 +601,6 @@ ParseStatus XtensaAsmParser::parseRegister(OperandVector &Operands,
627601
getLexer().UnLex(Buf[0]);
628602
return ParseStatus::NoMatch;
629603
}
630-
631-
if (!checkRegister(RegNo, getSTI().getFeatureBits()))
632-
return ParseStatus::NoMatch;
633-
634604
if (HadParens)
635605
Operands.push_back(XtensaOperand::createToken("(", FirstS));
636606
SMLoc S = getLoc();
@@ -732,7 +702,7 @@ bool XtensaAsmParser::ParseInstructionWithSR(ParseInstructionInfo &Info,
732702
if (RegNo == 0)
733703
RegNo = MatchRegisterAltName(RegName);
734704

735-
if (!checkRegister(RegNo, getSTI().getFeatureBits()))
705+
if (RegNo == 0)
736706
return Error(NameLoc, "invalid register name");
737707

738708
// Parse operand

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp

Lines changed: 2 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414

1515
#include "MCTargetDesc/XtensaMCTargetDesc.h"
1616
#include "TargetInfo/XtensaTargetInfo.h"
17-
#include "XtensaUtils.h"
1817
#include "llvm/MC/MCContext.h"
1918
#include "llvm/MC/MCDecoderOps.h"
2019
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
@@ -74,22 +73,17 @@ static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
7473
return MCDisassembler::Success;
7574
}
7675

77-
static const unsigned SRDecoderTable[] = {
78-
Xtensa::SAR, 3, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
76+
static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3};
7977

8078
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
8179
uint64_t Address,
82-
const MCDisassembler *Decoder) {
80+
const void *Decoder) {
8381
if (RegNo > 255)
8482
return MCDisassembler::Fail;
8583

8684
for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
8785
if (SRDecoderTable[i + 1] == RegNo) {
8886
unsigned Reg = SRDecoderTable[i];
89-
90-
if (!checkRegister(Reg, Decoder->getSubtargetInfo().getFeatureBits()))
91-
return MCDisassembler::Fail;
92-
9387
Inst.addOperand(MCOperand::createReg(Reg));
9488
return MCDisassembler::Success;
9589
}
@@ -216,29 +210,6 @@ static DecodeStatus decodeImm32n_95Operand(MCInst &Inst, uint64_t Imm,
216210
return MCDisassembler::Success;
217211
}
218212

219-
static DecodeStatus decodeImm8n_7Operand(MCInst &Inst, uint64_t Imm,
220-
int64_t Address, const void *Decoder) {
221-
assert(isUInt<4>(Imm) && "Invalid immediate");
222-
Inst.addOperand(MCOperand::createImm(Imm > 7 ? Imm - 16 : Imm));
223-
return MCDisassembler::Success;
224-
}
225-
226-
static DecodeStatus decodeImm64n_4nOperand(MCInst &Inst, uint64_t Imm,
227-
int64_t Address,
228-
const void *Decoder) {
229-
assert(isUInt<6>(Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");
230-
Inst.addOperand(MCOperand::createImm((~0x3f) | (Imm)));
231-
return MCDisassembler::Success;
232-
}
233-
234-
static DecodeStatus decodeEntry_Imm12OpValue(MCInst &Inst, uint64_t Imm,
235-
int64_t Address,
236-
const void *Decoder) {
237-
assert(isUInt<15>(Imm) && ((Imm & 0x7) == 0) && "Invalid immediate");
238-
Inst.addOperand(MCOperand::createImm(Imm));
239-
return MCDisassembler::Success;
240-
}
241-
242213
static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
243214
int64_t Address,
244215
const void *Decoder) {

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -264,28 +264,6 @@ void XtensaInstPrinter::printImm32n_95_AsmOperand(const MCInst *MI, int OpNum,
264264
printOperand(MI, OpNum, O);
265265
}
266266

267-
void XtensaInstPrinter::printImm8n_7_AsmOperand(const MCInst *MI, int OpNum,
268-
raw_ostream &O) {
269-
if (MI->getOperand(OpNum).isImm()) {
270-
int64_t Value = MI->getOperand(OpNum).getImm();
271-
assert((Value >= -8 && Value <= 7) &&
272-
"Invalid argument, value must be in ranges <-8,7>");
273-
O << Value;
274-
} else
275-
printOperand(MI, OpNum, O);
276-
}
277-
278-
void XtensaInstPrinter::printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum,
279-
raw_ostream &O) {
280-
if (MI->getOperand(OpNum).isImm()) {
281-
int64_t Value = MI->getOperand(OpNum).getImm();
282-
assert((Value >= -64 && Value <= -4) & ((Value & 0x3) == 0) &&
283-
"Invalid argument, value must be in ranges <-64,-4>");
284-
O << Value;
285-
} else
286-
printOperand(MI, OpNum, O);
287-
}
288-
289267
void XtensaInstPrinter::printOffset8m8_AsmOperand(const MCInst *MI, int OpNum,
290268
raw_ostream &O) {
291269
if (MI->getOperand(OpNum).isImm()) {
@@ -331,18 +309,6 @@ void XtensaInstPrinter::printOffset4m32_AsmOperand(const MCInst *MI, int OpNum,
331309
printOperand(MI, OpNum, O);
332310
}
333311

334-
void XtensaInstPrinter::printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum,
335-
raw_ostream &O) {
336-
if (MI->getOperand(OpNum).isImm()) {
337-
int64_t Value = MI->getOperand(OpNum).getImm();
338-
assert((Value >= 0 && Value <= 32760) &&
339-
"Invalid argument, value must be multiples of eight in range "
340-
"<0,32760>");
341-
O << Value;
342-
} else
343-
printOperand(MI, OpNum, O);
344-
}
345-
346312
void XtensaInstPrinter::printB4const_AsmOperand(const MCInst *MI, int OpNum,
347313
raw_ostream &O) {
348314
if (MI->getOperand(OpNum).isImm()) {

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,13 +60,10 @@ class XtensaInstPrinter : public MCInstPrinter {
6060
void printImm1_16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6161
void printImm1n_15_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6262
void printImm32n_95_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
63-
void printImm8n_7_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
64-
void printImm64n_4n_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6563
void printOffset8m8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6664
void printOffset8m16_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6765
void printOffset8m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
6866
void printOffset4m32_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
69-
void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7067
void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7168
void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7269
};

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp

Lines changed: 0 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -111,18 +111,6 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
111111
SmallVectorImpl<MCFixup> &Fixups,
112112
const MCSubtargetInfo &STI) const;
113113

114-
uint32_t getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
115-
SmallVectorImpl<MCFixup> &Fixups,
116-
const MCSubtargetInfo &STI) const;
117-
118-
uint32_t getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
119-
SmallVectorImpl<MCFixup> &Fixups,
120-
const MCSubtargetInfo &STI) const;
121-
122-
uint32_t getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
123-
SmallVectorImpl<MCFixup> &Fixups,
124-
const MCSubtargetInfo &STI) const;
125-
126114
uint32_t getShimm1_31OpValue(const MCInst &MI, unsigned OpNo,
127115
SmallVectorImpl<MCFixup> &Fixups,
128116
const MCSubtargetInfo &STI) const;
@@ -417,46 +405,6 @@ XtensaMCCodeEmitter::getImm32n_95OpValue(const MCInst &MI, unsigned OpNo,
417405
return Res;
418406
}
419407

420-
uint32_t
421-
XtensaMCCodeEmitter::getImm8n_7OpValue(const MCInst &MI, unsigned OpNo,
422-
SmallVectorImpl<MCFixup> &Fixups,
423-
const MCSubtargetInfo &STI) const {
424-
const MCOperand &MO = MI.getOperand(OpNo);
425-
int32_t Res = static_cast<int32_t>(MO.getImm());
426-
427-
assert(((Res >= -8) && (Res <= 7)) && "Unexpected operand value!");
428-
429-
if (Res < 0)
430-
return Res + 16;
431-
432-
return Res;
433-
}
434-
435-
uint32_t
436-
XtensaMCCodeEmitter::getImm64n_4nOpValue(const MCInst &MI, unsigned OpNo,
437-
SmallVectorImpl<MCFixup> &Fixups,
438-
const MCSubtargetInfo &STI) const {
439-
const MCOperand &MO = MI.getOperand(OpNo);
440-
int32_t Res = static_cast<int32_t>(MO.getImm());
441-
442-
assert(((Res >= -64) && (Res <= -4) && ((Res & 0x3) == 0)) &&
443-
"Unexpected operand value!");
444-
445-
return Res & 0x3f;
446-
}
447-
448-
uint32_t
449-
XtensaMCCodeEmitter::getEntry_Imm12OpValue(const MCInst &MI, unsigned OpNo,
450-
SmallVectorImpl<MCFixup> &Fixups,
451-
const MCSubtargetInfo &STI) const {
452-
const MCOperand &MO = MI.getOperand(OpNo);
453-
uint32_t res = static_cast<uint32_t>(MO.getImm());
454-
455-
assert(((res & 0x7) == 0) && "Unexpected operand value!");
456-
457-
return res;
458-
}
459-
460408
uint32_t
461409
XtensaMCCodeEmitter::getB4constOpValue(const MCInst &MI, unsigned OpNo,
462410
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/lib/Target/Xtensa/Xtensa.td

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,10 @@ include "llvm/Target/Target.td"
1717
//===----------------------------------------------------------------------===//
1818
// Subtarget Features.
1919
//===----------------------------------------------------------------------===//
20-
21-
include "XtensaFeatures.td"
22-
20+
def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
21+
"Enable Density instructions">;
22+
def HasDensity : Predicate<"Subtarget->hasDensity()">,
23+
AssemblerPredicate<(all_of FeatureDensity)>;
2324
//===----------------------------------------------------------------------===//
2425
// Xtensa supported processors.
2526
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Xtensa/XtensaFeatures.td

Lines changed: 0 additions & 14 deletions
This file was deleted.

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