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2 files changed

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llvm/lib/CodeGen/MachineCopyPropagation.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -707,10 +707,11 @@ bool MachineCopyPropagation::hasOverlappingMultipleDef(
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return false;
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}
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/// Return true if it is safe to update the users of the source register of the
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/// copy.
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/// Return true if it is safe to update all users of the \p CopySrc register
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/// in the given \p Copy instruction.
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bool MachineCopyPropagation::canUpdateSrcUsers(const MachineInstr &Copy,
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const MachineOperand &CopySrc) {
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assert(CopySrc.isReg() && "Expected a register operand");
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for (auto *SrcUser : Tracker.getSrcUsers(CopySrc.getReg(), *TRI)) {
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if (hasImplicitOverlap(*SrcUser, CopySrc))
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return false;
Lines changed: 58 additions & 0 deletions
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@@ -0,0 +1,58 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
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# Normal case
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---
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name: test1
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body: |
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bb.0:
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liveins: $w2
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; CHECK-LABEL: name: test1
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; CHECK: liveins: $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $w0 = MOVi32imm 5
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; CHECK-NEXT: renamable $w3 = ADDWrr renamable $w0, killed renamable $w2
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; CHECK-NEXT: RET_ReallyLR implicit killed $w0
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renamable $w1 = MOVi32imm 5
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renamable $w3 = ADDWrr renamable $w1, killed renamable $w2
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renamable $w0 = COPY killed renamable $w1
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RET_ReallyLR implicit killed $w0
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...
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# Not renamable use
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---
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name: test2
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body: |
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bb.0:
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liveins: $w2
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; CHECK-LABEL: name: test2
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; CHECK: liveins: $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $w1 = MOVi32imm 5
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; CHECK-NEXT: renamable $w3 = ADDWrr $w1, killed renamable $w2
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; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
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; CHECK-NEXT: RET_ReallyLR implicit killed $w0
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renamable $w1 = MOVi32imm 5
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renamable $w3 = ADDWrr $w1, killed renamable $w2
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renamable $w0 = COPY killed renamable $w1
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RET_ReallyLR implicit killed $w0
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...
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# Implicit use
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---
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name: test3
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body: |
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bb.0:
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liveins: $w2
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; CHECK-LABEL: name: test3
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; CHECK: liveins: $w2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $w1 = MOVi32imm 5
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; CHECK-NEXT: renamable $w3 = ADDWrr renamable $w1, killed renamable $w2, implicit $w1
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; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
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; CHECK-NEXT: RET_ReallyLR implicit killed $w0
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renamable $w1 = MOVi32imm 5
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renamable $w3 = ADDWrr renamable $w1, killed renamable $w2, implicit $w1
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renamable $w0 = COPY killed renamable $w1
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RET_ReallyLR implicit killed $w0
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...

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