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[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)
With the tag merging in place, we can safely change the default for +seq-cst-trailing-fence to the default, according to the recommendation in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc This tag changes the default for the feature flag, and moves to more consistent naming with respect to existing features.
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‎llvm/docs/ReleaseNotes.rst

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@@ -112,6 +112,11 @@ Changes to the RISC-V Backend
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* The experimental Ssqosid extension is supported.
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* Zacas is no longer experimental.
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* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.
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* The default atomics mapping was changed to emit an additional trailing fence
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for sequentially consistent stores, offering compatibility with a future
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mapping using load-acquire and store-release instructions while remaining
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fully compatible with objects produced prior to this change. The mapping
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(ABI) used is recorded as an ELF attribute.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

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@@ -77,9 +77,9 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
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}
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if (STI.hasFeature(RISCV::FeatureStdExtA)) {
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unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence)
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? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S
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: RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C;
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unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence)
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? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C
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: RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S;
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emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag);
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}
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}

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1216,10 +1216,10 @@ foreach i = {1-31} in
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def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
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"true", "Enable save/restore.">;
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def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
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"EnableSeqCstTrailingFence",
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"true",
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"Enable trailing fence for seq-cst store.">;
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def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence",
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"EnableTrailingSeqCstFence",
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"false",
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"Disable trailing fence for seq-cst store.">;
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def FeatureUnalignedScalarMem
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: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -20192,7 +20192,7 @@ Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
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if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
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return Builder.CreateFence(AtomicOrdering::Acquire);
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if (Subtarget.enableSeqCstTrailingFence() && isa<StoreInst>(Inst) &&
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if (Subtarget.enableTrailingSeqCstFence() && isa<StoreInst>(Inst) &&
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Ord == AtomicOrdering::SequentiallyConsistent)
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return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent);
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return nullptr;

‎llvm/test/CodeGen/RISCV/atomic-load-store.ll

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@@ -1,26 +1,26 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s
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; RUN: llc -mtriple=riscv32 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO-TRAILING-FENCE %s
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; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO-TRAILING-FENCE %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO-TRAILING-FENCE %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \
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; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s
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‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -129,8 +129,8 @@
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
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; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
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; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s
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; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
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; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
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; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s

‎llvm/test/CodeGen/RISCV/forced-atomics.ll

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@@ -1,12 +1,12 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
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; RUN: llc -mtriple=riscv32 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
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; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC
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; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
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; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
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; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC
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; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING
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; RUN: llc -mtriple=riscv64 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
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; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
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; RUN: llc -mtriple=riscv64 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC
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; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
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; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
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; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC
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; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING
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define i8 @load8(ptr %p) nounwind {
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; RV32-NO-ATOMIC-LABEL: load8:

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