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[ARM] Fix lowering for fp16 ops & add fp16 intrinsics test
1 parent 1359c8f commit 700169d

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2 files changed

+943
-8
lines changed

2 files changed

+943
-8
lines changed

llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 47 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1345,17 +1345,31 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
13451345
}
13461346

13471347
// FP16 often need to be promoted to call lib functions
1348+
// clang-format off
13481349
if (Subtarget->hasFullFP16()) {
1349-
for (auto Op : {ISD::FREM, ISD::FSIN, ISD::FCOS,
1350-
ISD::FTAN, ISD::FSINCOS, ISD::FPOWI,
1351-
ISD::FPOW, ISD::FEXP, ISD::FEXP2,
1352-
ISD::FEXP10, ISD::FLOG, ISD::FLOG10,
1353-
ISD::FLOG2, ISD::STRICT_FREM, ISD::STRICT_FSIN,
1354-
ISD::STRICT_FCOS, ISD::STRICT_FTAN, ISD::STRICT_FPOWI,
1355-
ISD::STRICT_FPOW, ISD::STRICT_FEXP, ISD::STRICT_FEXP2,
1356-
ISD::STRICT_FLOG, ISD::STRICT_FLOG10, ISD::STRICT_FLOG2}) {
1350+
for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI,
1351+
ISD::FCOS, ISD::FSIN, ISD::FSINCOS,
1352+
ISD::FSINCOSPI, ISD::FMODF, ISD::FACOS,
1353+
ISD::FASIN, ISD::FATAN, ISD::FATAN2,
1354+
ISD::FCOSH, ISD::FSINH, ISD::FTANH,
1355+
ISD::FTAN, ISD::FEXP, ISD::FEXP2,
1356+
ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
1357+
ISD::FLOG10, ISD::STRICT_FREM, ISD::STRICT_FPOW,
1358+
ISD::STRICT_FPOWI, ISD::STRICT_FCOS, ISD::STRICT_FSIN,
1359+
ISD::STRICT_FACOS, ISD::STRICT_FASIN, ISD::STRICT_FATAN,
1360+
ISD::STRICT_FATAN2, ISD::STRICT_FCOSH, ISD::STRICT_FSINH,
1361+
ISD::STRICT_FTANH, ISD::STRICT_FEXP, ISD::STRICT_FEXP2,
1362+
ISD::STRICT_FLOG, ISD::STRICT_FLOG2, ISD::STRICT_FLOG10,
1363+
ISD::STRICT_FTAN}) {
13571364
setOperationAction(Op, MVT::f16, Promote);
13581365
}
1366+
1367+
// Round-to-integer need custom lowering for fp16, as Promote doesn't work
1368+
// because the result type is integer.
1369+
for (auto Op : {ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
1370+
ISD::STRICT_LROUND, ISD::STRICT_LLROUND, ISD::STRICT_LRINT,
1371+
ISD::STRICT_LLRINT})
1372+
setOperationAction(Op, MVT::f16, Custom);
13591373

13601374
for (auto Op : {ISD::FROUND, ISD::FROUNDEVEN, ISD::FTRUNC,
13611375
ISD::FNEARBYINT, ISD::FRINT, ISD::FFLOOR,
@@ -1364,6 +1378,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
13641378
ISD::STRICT_FFLOOR, ISD::STRICT_FCEIL}) {
13651379
setOperationAction(Op, MVT::f16, Legal);
13661380
}
1381+
// clang-format on
13671382

13681383
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
13691384
}
@@ -10716,6 +10731,30 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1071610731
case ISD::UCMP:
1071710732
case ISD::SCMP:
1071810733
return LowerCMP(Op, DAG);
10734+
case ISD::LRINT:
10735+
case ISD::LLRINT:
10736+
case ISD::LROUND:
10737+
case ISD::LLROUND: {
10738+
assert((Op.getOperand(0).getValueType() == MVT::f16 ||
10739+
Op.getOperand(1).getValueType() == MVT::bf16) &&
10740+
"Expected custom lowering of rounding operations only for f16");
10741+
SDLoc DL(Op);
10742+
SDValue Ext = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0));
10743+
return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(), Ext);
10744+
}
10745+
case ISD::STRICT_LROUND:
10746+
case ISD::STRICT_LLROUND:
10747+
case ISD::STRICT_LRINT:
10748+
case ISD::STRICT_LLRINT: {
10749+
assert((Op.getOperand(1).getValueType() == MVT::f16 ||
10750+
Op.getOperand(1).getValueType() == MVT::bf16) &&
10751+
"Expected custom lowering of rounding operations only for f16");
10752+
SDLoc DL(Op);
10753+
SDValue Ext = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
10754+
{Op.getOperand(0), Op.getOperand(1)});
10755+
return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
10756+
{Ext.getValue(1), Ext.getValue(0)});
10757+
}
1071910758
}
1072010759
}
1072110760

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