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remove scalable build vectors
1 parent f219997 commit 6f5d091

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2 files changed

+5
-14
lines changed

2 files changed

+5
-14
lines changed

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
473473
} else {
474474
// Vector was split, and elements promoted to a wider type.
475475
// FIXME: Should handle floating point promotions.
476-
LLT BVType = LLT::vector(LLTy.getElementCount(), PartLLT);
476+
LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
477477
auto BV = B.buildBuildVector(BVType, Regs);
478478
B.buildTrunc(OrigRegs[0], BV);
479479
}

llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1281,19 +1281,10 @@ MachineIRBuilder::buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
12811281
SrcOps[0].getLLTTy(*getMRI());
12821282
}) &&
12831283
"type mismatch in input list");
1284-
if (DstOps[0].getLLTTy(*getMRI()).isScalable())
1285-
assert((TypeSize::ScalarTy)SrcOps.size() *
1286-
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() >=
1287-
DstOps[0]
1288-
.getLLTTy(*getMRI())
1289-
.getSizeInBits()
1290-
.getKnownMinValue() &&
1291-
"input scalars does not cover the output vector register");
1292-
else
1293-
assert((TypeSize::ScalarTy)SrcOps.size() *
1294-
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1295-
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1296-
"input scalars do not exactly cover the output vector register");
1284+
assert((TypeSize::ScalarTy)SrcOps.size() *
1285+
SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
1286+
DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&
1287+
"input scalars do not exactly cover the output vector register");
12971288
break;
12981289
}
12991290
case TargetOpcode::G_BUILD_VECTOR_TRUNC: {

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