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[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)
 (and X, (C<<12|0xfff)) -> (ANDN X, ~C<<12) (or X, (C<<12|0xfff)) -> (ORN X, ~C<<12) (xor X, (C<<12|0xfff)) -> (XNOR X, ~C<<12) Emits better code, typically by avoiding an `ADDI HI, -1` instruction. Co-authored-by: Craig Topper <[email protected]>
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-102
lines changed

5 files changed

+92
-102
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3236,6 +3236,35 @@ bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
32363236
return false;
32373237
}
32383238

3239+
bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
3240+
if (!isa<ConstantSDNode>(N))
3241+
return false;
3242+
3243+
int64_t Imm = cast<ConstantSDNode>(N)->getSExtValue();
3244+
if ((Imm & 0xfff) != 0xfff || Imm == -1)
3245+
return false;
3246+
3247+
for (const SDNode *U : N->users()) {
3248+
if (!ISD::isBitwiseLogicOp(U->getOpcode()))
3249+
return false;
3250+
}
3251+
3252+
// For 32-bit signed constants we already know it's a win: LUI+ADDI vs LUI.
3253+
// For 64-bit constants, the instruction sequences get complex,
3254+
// so we select inverted only if it's cheaper.
3255+
if (!isInt<32>(Imm)) {
3256+
int OrigImmCost = RISCVMatInt::getIntMatCost(APInt(64, Imm), 64, *Subtarget,
3257+
/*CompressionCost=*/true);
3258+
int NegImmCost = RISCVMatInt::getIntMatCost(APInt(64, ~Imm), 64, *Subtarget,
3259+
/*CompressionCost=*/true);
3260+
if (OrigImmCost <= NegImmCost)
3261+
return false;
3262+
}
3263+
3264+
Val = selectImm(CurDAG, SDLoc(N), N->getSimpleValueType(0), ~Imm, *Subtarget);
3265+
return true;
3266+
}
3267+
32393268
static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
32403269
unsigned Bits,
32413270
const TargetInstrInfo *TII) {

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
119119
return selectSHXADD_UWOp(N, ShAmt, Val);
120120
}
121121

122+
bool selectInvLogicImm(SDValue N, SDValue &Val);
123+
122124
bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
123125
const unsigned Depth = 0) const;
124126
bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 8); }

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -475,10 +475,16 @@ def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>;
475475
// Codegen patterns
476476
//===----------------------------------------------------------------------===//
477477

478+
def invLogicImm : ComplexPattern<XLenVT, 1, "selectInvLogicImm", [], [], 0>;
479+
478480
let Predicates = [HasStdExtZbbOrZbkb] in {
479481
def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
480482
def : Pat<(XLenVT (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
481483
def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
484+
485+
def : Pat<(XLenVT (and GPR:$rs1, invLogicImm:$rs2)), (ANDN GPR:$rs1, invLogicImm:$rs2)>;
486+
def : Pat<(XLenVT (or GPR:$rs1, invLogicImm:$rs2)), (ORN GPR:$rs1, invLogicImm:$rs2)>;
487+
def : Pat<(XLenVT (xor GPR:$rs1, invLogicImm:$rs2)), (XNOR GPR:$rs1, invLogicImm:$rs2)>;
482488
} // Predicates = [HasStdExtZbbOrZbkb]
483489

484490
let Predicates = [HasStdExtZbbOrZbkb] in {

‎llvm/test/CodeGen/RISCV/pr84653_pr85190.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,7 @@ define i1 @pr84653(i32 %x) {
2121
; CHECK-ZBB: # %bb.0:
2222
; CHECK-ZBB-NEXT: sext.w a1, a0
2323
; CHECK-ZBB-NEXT: lui a2, 524288
24-
; CHECK-ZBB-NEXT: addi a2, a2, -1
25-
; CHECK-ZBB-NEXT: xor a0, a0, a2
24+
; CHECK-ZBB-NEXT: xnor a0, a0, a2
2625
; CHECK-ZBB-NEXT: sext.w a0, a0
2726
; CHECK-ZBB-NEXT: max a0, a0, zero
2827
; CHECK-ZBB-NEXT: slt a0, a0, a1
@@ -82,8 +81,7 @@ define i1 @select_to_or(i32 %x) {
8281
; CHECK-ZBB: # %bb.0:
8382
; CHECK-ZBB-NEXT: sext.w a1, a0
8483
; CHECK-ZBB-NEXT: lui a2, 524288
85-
; CHECK-ZBB-NEXT: addi a2, a2, -1
86-
; CHECK-ZBB-NEXT: xor a0, a0, a2
84+
; CHECK-ZBB-NEXT: xnor a0, a0, a2
8785
; CHECK-ZBB-NEXT: sext.w a0, a0
8886
; CHECK-ZBB-NEXT: min a0, a0, zero
8987
; CHECK-ZBB-NEXT: slt a0, a0, a1

‎llvm/test/CodeGen/RISCV/zbb-logic-neg-imm.ll‎

Lines changed: 53 additions & 98 deletions
Original file line numberDiff line numberDiff line change
@@ -9,91 +9,57 @@
99
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,ZBS
1010

1111
define i32 @and0xabcdefff(i32 %x) {
12-
; RV32-LABEL: and0xabcdefff:
13-
; RV32: # %bb.0:
14-
; RV32-NEXT: lui a1, 703711
15-
; RV32-NEXT: addi a1, a1, -1
16-
; RV32-NEXT: and a0, a0, a1
17-
; RV32-NEXT: ret
18-
;
19-
; RV64-LABEL: and0xabcdefff:
20-
; RV64: # %bb.0:
21-
; RV64-NEXT: lui a1, 703711
22-
; RV64-NEXT: addiw a1, a1, -1
23-
; RV64-NEXT: and a0, a0, a1
24-
; RV64-NEXT: ret
12+
; CHECK-LABEL: and0xabcdefff:
13+
; CHECK: # %bb.0:
14+
; CHECK-NEXT: lui a1, 344865
15+
; CHECK-NEXT: andn a0, a0, a1
16+
; CHECK-NEXT: ret
2517
%and = and i32 %x, -1412567041
2618
ret i32 %and
2719
}
2820

2921
define i32 @orlow13(i32 %x) {
30-
; RV32-LABEL: orlow13:
31-
; RV32: # %bb.0:
32-
; RV32-NEXT: lui a1, 2
33-
; RV32-NEXT: addi a1, a1, -1
34-
; RV32-NEXT: or a0, a0, a1
35-
; RV32-NEXT: ret
36-
;
37-
; RV64-LABEL: orlow13:
38-
; RV64: # %bb.0:
39-
; RV64-NEXT: lui a1, 2
40-
; RV64-NEXT: addiw a1, a1, -1
41-
; RV64-NEXT: or a0, a0, a1
42-
; RV64-NEXT: ret
22+
; CHECK-LABEL: orlow13:
23+
; CHECK: # %bb.0:
24+
; CHECK-NEXT: lui a1, 1048574
25+
; CHECK-NEXT: orn a0, a0, a1
26+
; CHECK-NEXT: ret
4327
%or = or i32 %x, 8191
4428
ret i32 %or
4529
}
4630

4731
define i64 @orlow24(i64 %x) {
4832
; RV32-LABEL: orlow24:
4933
; RV32: # %bb.0:
50-
; RV32-NEXT: lui a2, 4096
51-
; RV32-NEXT: addi a2, a2, -1
52-
; RV32-NEXT: or a0, a0, a2
34+
; RV32-NEXT: lui a2, 1044480
35+
; RV32-NEXT: orn a0, a0, a2
5336
; RV32-NEXT: ret
5437
;
5538
; RV64-LABEL: orlow24:
5639
; RV64: # %bb.0:
57-
; RV64-NEXT: lui a1, 4096
58-
; RV64-NEXT: addiw a1, a1, -1
59-
; RV64-NEXT: or a0, a0, a1
40+
; RV64-NEXT: lui a1, 1044480
41+
; RV64-NEXT: orn a0, a0, a1
6042
; RV64-NEXT: ret
6143
%or = or i64 %x, 16777215
6244
ret i64 %or
6345
}
6446

6547
define i32 @xorlow16(i32 %x) {
66-
; RV32-LABEL: xorlow16:
67-
; RV32: # %bb.0:
68-
; RV32-NEXT: lui a1, 16
69-
; RV32-NEXT: addi a1, a1, -1
70-
; RV32-NEXT: xor a0, a0, a1
71-
; RV32-NEXT: ret
72-
;
73-
; RV64-LABEL: xorlow16:
74-
; RV64: # %bb.0:
75-
; RV64-NEXT: lui a1, 16
76-
; RV64-NEXT: addiw a1, a1, -1
77-
; RV64-NEXT: xor a0, a0, a1
78-
; RV64-NEXT: ret
48+
; CHECK-LABEL: xorlow16:
49+
; CHECK: # %bb.0:
50+
; CHECK-NEXT: lui a1, 1048560
51+
; CHECK-NEXT: xnor a0, a0, a1
52+
; CHECK-NEXT: ret
7953
%xor = xor i32 %x, 65535
8054
ret i32 %xor
8155
}
8256

8357
define i32 @xorlow31(i32 %x) {
84-
; RV32-LABEL: xorlow31:
85-
; RV32: # %bb.0:
86-
; RV32-NEXT: lui a1, 524288
87-
; RV32-NEXT: addi a1, a1, -1
88-
; RV32-NEXT: xor a0, a0, a1
89-
; RV32-NEXT: ret
90-
;
91-
; RV64-LABEL: xorlow31:
92-
; RV64: # %bb.0:
93-
; RV64-NEXT: lui a1, 524288
94-
; RV64-NEXT: addiw a1, a1, -1
95-
; RV64-NEXT: xor a0, a0, a1
96-
; RV64-NEXT: ret
58+
; CHECK-LABEL: xorlow31:
59+
; CHECK: # %bb.0:
60+
; CHECK-NEXT: lui a1, 524288
61+
; CHECK-NEXT: xnor a0, a0, a1
62+
; CHECK-NEXT: ret
9763
%xor = xor i32 %x, 2147483647
9864
ret i32 %xor
9965
}
@@ -164,8 +130,7 @@ define void @orarray100(ptr %a) {
164130
; RV32: # %bb.0: # %entry
165131
; RV32-NEXT: li a1, 0
166132
; RV32-NEXT: li a2, 0
167-
; RV32-NEXT: lui a3, 16
168-
; RV32-NEXT: addi a3, a3, -1
133+
; RV32-NEXT: lui a3, 1048560
169134
; RV32-NEXT: .LBB8_1: # %for.body
170135
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
171136
; RV32-NEXT: slli a4, a1, 2
@@ -175,7 +140,7 @@ define void @orarray100(ptr %a) {
175140
; RV32-NEXT: seqz a6, a1
176141
; RV32-NEXT: add a2, a2, a6
177142
; RV32-NEXT: xori a6, a1, 100
178-
; RV32-NEXT: or a5, a5, a3
143+
; RV32-NEXT: orn a5, a5, a3
179144
; RV32-NEXT: or a6, a6, a2
180145
; RV32-NEXT: sw a5, 0(a4)
181146
; RV32-NEXT: bnez a6, .LBB8_1
@@ -185,12 +150,11 @@ define void @orarray100(ptr %a) {
185150
; RV64-LABEL: orarray100:
186151
; RV64: # %bb.0: # %entry
187152
; RV64-NEXT: addi a1, a0, 400
188-
; RV64-NEXT: lui a2, 16
189-
; RV64-NEXT: addi a2, a2, -1
153+
; RV64-NEXT: lui a2, 1048560
190154
; RV64-NEXT: .LBB8_1: # %for.body
191155
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
192156
; RV64-NEXT: lw a3, 0(a0)
193-
; RV64-NEXT: or a3, a3, a2
157+
; RV64-NEXT: orn a3, a3, a2
194158
; RV64-NEXT: sw a3, 0(a0)
195159
; RV64-NEXT: addi a0, a0, 4
196160
; RV64-NEXT: bne a0, a1, .LBB8_1
@@ -216,17 +180,16 @@ for.body:
216180
define void @orarray3(ptr %a) {
217181
; CHECK-LABEL: orarray3:
218182
; CHECK: # %bb.0:
219-
; CHECK-NEXT: lui a1, 16
220-
; CHECK-NEXT: lw a2, 0(a0)
221-
; CHECK-NEXT: lw a3, 4(a0)
222-
; CHECK-NEXT: lw a4, 8(a0)
223-
; CHECK-NEXT: addi a1, a1, -1
224-
; CHECK-NEXT: or a2, a2, a1
225-
; CHECK-NEXT: or a3, a3, a1
226-
; CHECK-NEXT: or a1, a4, a1
227-
; CHECK-NEXT: sw a2, 0(a0)
228-
; CHECK-NEXT: sw a3, 4(a0)
229-
; CHECK-NEXT: sw a1, 8(a0)
183+
; CHECK-NEXT: lw a1, 0(a0)
184+
; CHECK-NEXT: lw a2, 4(a0)
185+
; CHECK-NEXT: lw a3, 8(a0)
186+
; CHECK-NEXT: lui a4, 1048560
187+
; CHECK-NEXT: orn a1, a1, a4
188+
; CHECK-NEXT: orn a2, a2, a4
189+
; CHECK-NEXT: orn a3, a3, a4
190+
; CHECK-NEXT: sw a1, 0(a0)
191+
; CHECK-NEXT: sw a2, 4(a0)
192+
; CHECK-NEXT: sw a3, 8(a0)
230193
; CHECK-NEXT: ret
231194
%1 = load i32, ptr %a, align 4
232195
%or = or i32 %1, 65535
@@ -279,16 +242,14 @@ define i32 @compl(i32 %x) {
279242
define i32 @orlow12(i32 %x) {
280243
; NOZBS32-LABEL: orlow12:
281244
; NOZBS32: # %bb.0:
282-
; NOZBS32-NEXT: lui a1, 1
283-
; NOZBS32-NEXT: addi a1, a1, -1
284-
; NOZBS32-NEXT: or a0, a0, a1
245+
; NOZBS32-NEXT: lui a1, 1048575
246+
; NOZBS32-NEXT: orn a0, a0, a1
285247
; NOZBS32-NEXT: ret
286248
;
287249
; NOZBS64-LABEL: orlow12:
288250
; NOZBS64: # %bb.0:
289-
; NOZBS64-NEXT: lui a1, 1
290-
; NOZBS64-NEXT: addiw a1, a1, -1
291-
; NOZBS64-NEXT: or a0, a0, a1
251+
; NOZBS64-NEXT: lui a1, 1048575
252+
; NOZBS64-NEXT: orn a0, a0, a1
292253
; NOZBS64-NEXT: ret
293254
;
294255
; ZBS-LABEL: orlow12:
@@ -303,16 +264,14 @@ define i32 @orlow12(i32 %x) {
303264
define i32 @xorlow12(i32 %x) {
304265
; NOZBS32-LABEL: xorlow12:
305266
; NOZBS32: # %bb.0:
306-
; NOZBS32-NEXT: lui a1, 1
307-
; NOZBS32-NEXT: addi a1, a1, -1
308-
; NOZBS32-NEXT: xor a0, a0, a1
267+
; NOZBS32-NEXT: lui a1, 1048575
268+
; NOZBS32-NEXT: xnor a0, a0, a1
309269
; NOZBS32-NEXT: ret
310270
;
311271
; NOZBS64-LABEL: xorlow12:
312272
; NOZBS64: # %bb.0:
313-
; NOZBS64-NEXT: lui a1, 1
314-
; NOZBS64-NEXT: addiw a1, a1, -1
315-
; NOZBS64-NEXT: xor a0, a0, a1
273+
; NOZBS64-NEXT: lui a1, 1048575
274+
; NOZBS64-NEXT: xnor a0, a0, a1
316275
; NOZBS64-NEXT: ret
317276
;
318277
; ZBS-LABEL: xorlow12:
@@ -327,18 +286,16 @@ define i32 @xorlow12(i32 %x) {
327286
define i64 @andimm64(i64 %x) {
328287
; RV32-LABEL: andimm64:
329288
; RV32: # %bb.0:
330-
; RV32-NEXT: lui a1, 1044496
331-
; RV32-NEXT: addi a1, a1, -1
332-
; RV32-NEXT: and a0, a0, a1
289+
; RV32-NEXT: lui a1, 4080
290+
; RV32-NEXT: andn a0, a0, a1
333291
; RV32-NEXT: li a1, 0
334292
; RV32-NEXT: ret
335293
;
336294
; RV64-LABEL: andimm64:
337295
; RV64: # %bb.0:
338-
; RV64-NEXT: lui a1, 65281
296+
; RV64-NEXT: lui a1, 983295
339297
; RV64-NEXT: slli a1, a1, 4
340-
; RV64-NEXT: addi a1, a1, -1
341-
; RV64-NEXT: and a0, a0, a1
298+
; RV64-NEXT: andn a0, a0, a1
342299
; RV64-NEXT: ret
343300
%and = and i64 %x, 4278255615
344301
ret i64 %and
@@ -347,19 +304,17 @@ define i64 @andimm64(i64 %x) {
347304
define i64 @andimm64srli(i64 %x) {
348305
; RV32-LABEL: andimm64srli:
349306
; RV32: # %bb.0:
307+
; RV32-NEXT: lui a2, 1040384
308+
; RV32-NEXT: orn a0, a0, a2
350309
; RV32-NEXT: lui a2, 917504
351310
; RV32-NEXT: or a1, a1, a2
352-
; RV32-NEXT: lui a2, 8192
353-
; RV32-NEXT: addi a2, a2, -1
354-
; RV32-NEXT: or a0, a0, a2
355311
; RV32-NEXT: ret
356312
;
357313
; RV64-LABEL: andimm64srli:
358314
; RV64: # %bb.0:
359315
; RV64-NEXT: lui a1, 983040
360316
; RV64-NEXT: srli a1, a1, 3
361-
; RV64-NEXT: not a1, a1
362-
; RV64-NEXT: or a0, a0, a1
317+
; RV64-NEXT: orn a0, a0, a1
363318
; RV64-NEXT: ret
364319
%or = or i64 %x, -2305843009180139521
365320
ret i64 %or

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