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| 1 | +// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common %s | FileCheck %s |
| 2 | + |
| 3 | +include "llvm/Target/Target.td" |
| 4 | +include "GlobalISelEmitterCommon.td" |
| 5 | + |
| 6 | +def undef_tied : OperandWithDefaultOps<untyped, (ops (i32 undef_tied_input))> { |
| 7 | + let MIOperandInfo = (ops GPR32:$inactive); |
| 8 | +} |
| 9 | + |
| 10 | +let Constraints = "$opt.inactive = $rd" in |
| 11 | +def I1 : I<(outs GPR32:$rd), (ins GPR32:$rs, undef_tied:$opt), |
| 12 | + [(set GPR32:$rd, (abs i32:$rs))]>; |
| 13 | + |
| 14 | +// CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$rs) => (I1:{ *:[i32] } i32:{ *:[i32] }:$rs) |
| 15 | +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16 | +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17 | +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18 | +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1), |
| 19 | +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd] |
| 20 | +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs |
| 21 | +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22 | +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, |
| 23 | +// CHECK-NEXT: // GIR_Coverage, 0, |
| 24 | +// CHECK-NEXT: GIR_EraseRootFromParent_Done, |
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