Skip to content

Commit 6cbc64e

Browse files
authored
[TableGen][GISel] Fix IMPLICIT_DEF operand being added as a use (#121283)
`IMPLICIT_DEF` has one operand that is a def, not a use.
1 parent db7123f commit 6cbc64e

File tree

2 files changed

+25
-1
lines changed

2 files changed

+25
-1
lines changed
Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
// RUN: llvm-tblgen -gen-global-isel -I %p/../../../include -I %p/../Common %s | FileCheck %s
2+
3+
include "llvm/Target/Target.td"
4+
include "GlobalISelEmitterCommon.td"
5+
6+
def undef_tied : OperandWithDefaultOps<untyped, (ops (i32 undef_tied_input))> {
7+
let MIOperandInfo = (ops GPR32:$inactive);
8+
}
9+
10+
let Constraints = "$opt.inactive = $rd" in
11+
def I1 : I<(outs GPR32:$rd), (ins GPR32:$rs, undef_tied:$opt),
12+
[(set GPR32:$rd, (abs i32:$rs))]>;
13+
14+
// CHECK-LABEL: // (abs:{ *:[i32] } i32:{ *:[i32] }:$rs) => (I1:{ *:[i32] } i32:{ *:[i32] }:$rs)
15+
// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16+
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17+
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18+
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::I1),
19+
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20+
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // rs
21+
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22+
// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
23+
// CHECK-NEXT: // GIR_Coverage, 0,
24+
// CHECK-NEXT: GIR_EraseRootFromParent_Done,

llvm/utils/TableGen/GlobalISelEmitter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1756,7 +1756,7 @@ Error GlobalISelEmitter::importDefaultOperandRenderers(
17561756
&Target.getInstruction(RK.getDef("IMPLICIT_DEF")));
17571757
BuildMIAction &IDMIBuilder =
17581758
*static_cast<BuildMIAction *>(InsertPt->get());
1759-
IDMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
1759+
IDMIBuilder.addRenderer<TempRegRenderer>(TempRegID, /*IsDef=*/true);
17601760
DstMIBuilder.addRenderer<TempRegRenderer>(TempRegID);
17611761
} else {
17621762
DstMIBuilder.addRenderer<AddRegisterRenderer>(Target, Def);

0 commit comments

Comments
 (0)