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davemgreendavemgreen
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[AArch64] Materialize constants via fneg. (#80641)
This is something that is already done as a special case for copysign, this patch extends it to be more generally applied. If we are trying to matrialize a negative constant (notably -0.0, 0x80000000), then there may be no movi encoding that creates the immediate, but a fneg(movi) might. Some of the existing patterns for RADDHN needed to be adjusted to keep them in line with the new immediates.
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9 files changed

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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 68 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -12935,42 +12935,74 @@ static SDValue NormalizeBuildVector(SDValue Op,
1293512935
return DAG.getBuildVector(VT, dl, Ops);
1293612936
}
1293712937

12938-
static SDValue ConstantBuildVector(SDValue Op, SelectionDAG &DAG) {
12938+
static SDValue ConstantBuildVector(SDValue Op, SelectionDAG &DAG,
12939+
const AArch64Subtarget *ST) {
1293912940
EVT VT = Op.getValueType();
12941+
assert((VT.getSizeInBits() == 64 || VT.getSizeInBits() == 128) &&
12942+
"Expected a legal NEON vector");
1294012943

1294112944
APInt DefBits(VT.getSizeInBits(), 0);
1294212945
APInt UndefBits(VT.getSizeInBits(), 0);
1294312946
BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
1294412947
if (resolveBuildVector(BVN, DefBits, UndefBits)) {
12945-
SDValue NewOp;
12946-
if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
12947-
(NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12948-
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
12949-
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12950-
(NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
12951-
(NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
12952-
return NewOp;
12953-
12954-
DefBits = ~DefBits;
12955-
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
12956-
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
12957-
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
12958-
return NewOp;
12959-
12960-
DefBits = UndefBits;
12961-
if ((NewOp = tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
12962-
(NewOp = tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12963-
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
12964-
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12965-
(NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
12966-
(NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
12967-
return NewOp;
12948+
auto TryMOVIWithBits = [&](APInt DefBits) {
12949+
SDValue NewOp;
12950+
if ((NewOp =
12951+
tryAdvSIMDModImm64(AArch64ISD::MOVIedit, Op, DAG, DefBits)) ||
12952+
(NewOp =
12953+
tryAdvSIMDModImm32(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12954+
(NewOp =
12955+
tryAdvSIMDModImm321s(AArch64ISD::MOVImsl, Op, DAG, DefBits)) ||
12956+
(NewOp =
12957+
tryAdvSIMDModImm16(AArch64ISD::MOVIshift, Op, DAG, DefBits)) ||
12958+
(NewOp = tryAdvSIMDModImm8(AArch64ISD::MOVI, Op, DAG, DefBits)) ||
12959+
(NewOp = tryAdvSIMDModImmFP(AArch64ISD::FMOV, Op, DAG, DefBits)))
12960+
return NewOp;
12961+
12962+
APInt NotDefBits = ~DefBits;
12963+
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG,
12964+
NotDefBits)) ||
12965+
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG,
12966+
NotDefBits)) ||
12967+
(NewOp =
12968+
tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, NotDefBits)))
12969+
return NewOp;
12970+
return SDValue();
12971+
};
12972+
if (SDValue R = TryMOVIWithBits(DefBits))
12973+
return R;
12974+
if (SDValue R = TryMOVIWithBits(UndefBits))
12975+
return R;
1296812976

12969-
DefBits = ~UndefBits;
12970-
if ((NewOp = tryAdvSIMDModImm32(AArch64ISD::MVNIshift, Op, DAG, DefBits)) ||
12971-
(NewOp = tryAdvSIMDModImm321s(AArch64ISD::MVNImsl, Op, DAG, DefBits)) ||
12972-
(NewOp = tryAdvSIMDModImm16(AArch64ISD::MVNIshift, Op, DAG, DefBits)))
12973-
return NewOp;
12977+
// See if a fneg of the constant can be materialized with a MOVI, etc
12978+
auto TryWithFNeg = [&](APInt DefBits, MVT FVT) {
12979+
// FNegate each sub-element of the constant
12980+
assert(VT.getSizeInBits() % FVT.getScalarSizeInBits() == 0);
12981+
APInt Neg = APInt::getHighBitsSet(FVT.getSizeInBits(), 1)
12982+
.zext(VT.getSizeInBits());
12983+
APInt NegBits(VT.getSizeInBits(), 0);
12984+
unsigned NumElts = VT.getSizeInBits() / FVT.getScalarSizeInBits();
12985+
for (unsigned i = 0; i < NumElts; i++)
12986+
NegBits |= Neg << (FVT.getScalarSizeInBits() * i);
12987+
NegBits = DefBits ^ NegBits;
12988+
12989+
// Try to create the new constants with MOVI, and if so generate a fneg
12990+
// for it.
12991+
if (SDValue NewOp = TryMOVIWithBits(NegBits)) {
12992+
SDLoc DL(Op);
12993+
MVT VFVT = NumElts == 1 ? FVT : MVT::getVectorVT(FVT, NumElts);
12994+
return DAG.getNode(
12995+
AArch64ISD::NVCAST, DL, VT,
12996+
DAG.getNode(ISD::FNEG, DL, VFVT,
12997+
DAG.getNode(AArch64ISD::NVCAST, DL, VFVT, NewOp)));
12998+
}
12999+
return SDValue();
13000+
};
13001+
SDValue R;
13002+
if ((R = TryWithFNeg(DefBits, MVT::f32)) ||
13003+
(R = TryWithFNeg(DefBits, MVT::f64)) ||
13004+
(ST->hasFullFP16() && (R = TryWithFNeg(DefBits, MVT::f16))))
13005+
return R;
1297413006
}
1297513007

1297613008
return SDValue();
@@ -13019,7 +13051,7 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
1301913051
return Op;
1302013052
}
1302113053

13022-
if (SDValue V = ConstantBuildVector(Op, DAG))
13054+
if (SDValue V = ConstantBuildVector(Op, DAG, Subtarget))
1302313055
return V;
1302413056

1302513057
// Scan through the operands to find some interesting properties we can
@@ -13244,7 +13276,7 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
1324413276
ConstantValueAPInt = C->getAPIntValue().zextOrTrunc(BitSize);
1324513277
if (!isNullConstant(ConstantValue) && !isNullFPConstant(ConstantValue) &&
1324613278
!ConstantValueAPInt.isAllOnes()) {
13247-
Val = ConstantBuildVector(Val, DAG);
13279+
Val = ConstantBuildVector(Val, DAG, Subtarget);
1324813280
if (!Val)
1324913281
// Otherwise, materialize the constant and splat it.
1325013282
Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
@@ -23145,9 +23177,12 @@ static SDValue performDUPCombine(SDNode *N,
2314523177
}
2314623178

2314723179
/// Get rid of unnecessary NVCASTs (that don't change the type).
23148-
static SDValue performNVCASTCombine(SDNode *N) {
23180+
static SDValue performNVCASTCombine(SDNode *N, SelectionDAG &DAG) {
2314923181
if (N->getValueType(0) == N->getOperand(0).getValueType())
2315023182
return N->getOperand(0);
23183+
if (N->getOperand(0).getOpcode() == AArch64ISD::NVCAST)
23184+
return DAG.getNode(AArch64ISD::NVCAST, SDLoc(N), N->getValueType(0),
23185+
N->getOperand(0).getOperand(0));
2315123186

2315223187
return SDValue();
2315323188
}
@@ -24141,7 +24176,7 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2414124176
case AArch64ISD::DUPLANE128:
2414224177
return performDupLane128Combine(N, DAG);
2414324178
case AArch64ISD::NVCAST:
24144-
return performNVCASTCombine(N);
24179+
return performNVCASTCombine(N, DAG);
2414524180
case AArch64ISD::SPLICE:
2414624181
return performSpliceCombine(N, DAG);
2414724182
case AArch64ISD::UUNPKLO:

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7595,13 +7595,17 @@ defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
75957595
defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
75967596
TriOpFrag<(add_and_or_is_add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
75977597

7598+
def VImm0080: PatLeaf<(AArch64movi_shift (i32 128), (i32 0))>;
7599+
def VImm00008000: PatLeaf<(AArch64movi_shift (i32 128), (i32 8))>;
7600+
def VImm0000000080000000: PatLeaf<(AArch64NvCast (v2f64 (fneg (AArch64NvCast (v4i32 (AArch64movi_shift (i32 128), (i32 24)))))))>;
7601+
75987602
// RADDHN patterns for when RSHRN shifts by half the size of the vector element
7599-
def : Pat<(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), (AArch64movi_shift (i32 128), (i32 0))), (i32 8)))),
7603+
def : Pat<(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), VImm0080), (i32 8)))),
76007604
(RADDHNv8i16_v8i8 V128:$Vn, (v8i16 (MOVIv2d_ns (i32 0))))>;
7601-
def : Pat<(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), (AArch64movi_shift (i32 128), (i32 8))), (i32 16)))),
7605+
def : Pat<(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))),
76027606
(RADDHNv4i32_v4i16 V128:$Vn, (v4i32 (MOVIv2d_ns (i32 0))))>;
76037607
let AddedComplexity = 5 in
7604-
def : Pat<(v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), (AArch64dup (i64 2147483648))), (i32 32)))),
7608+
def : Pat<(v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), VImm0000000080000000), (i32 32)))),
76057609
(RADDHNv2i64_v2i32 V128:$Vn, (v2i64 (MOVIv2d_ns (i32 0))))>;
76067610
def : Pat<(v8i8 (int_aarch64_neon_rshrn (v8i16 V128:$Vn), (i32 8))),
76077611
(RADDHNv8i16_v8i8 V128:$Vn, (v8i16 (MOVIv2d_ns (i32 0))))>;
@@ -7613,20 +7617,20 @@ def : Pat<(v2i32 (int_aarch64_neon_rshrn (v2i64 V128:$Vn), (i32 32))),
76137617
// RADDHN2 patterns for when RSHRN shifts by half the size of the vector element
76147618
def : Pat<(v16i8 (concat_vectors
76157619
(v8i8 V64:$Vd),
7616-
(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), (AArch64movi_shift (i32 128), (i32 0))), (i32 8)))))),
7620+
(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), VImm0080), (i32 8)))))),
76177621
(RADDHNv8i16_v16i8
76187622
(INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,
76197623
(v8i16 (MOVIv2d_ns (i32 0))))>;
76207624
def : Pat<(v8i16 (concat_vectors
76217625
(v4i16 V64:$Vd),
7622-
(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), (AArch64movi_shift (i32 128), (i32 8))), (i32 16)))))),
7626+
(v4i16 (trunc (AArch64vlshr (add (v4i32 V128:$Vn), VImm00008000), (i32 16)))))),
76237627
(RADDHNv4i32_v8i16
76247628
(INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,
76257629
(v4i32 (MOVIv2d_ns (i32 0))))>;
76267630
let AddedComplexity = 5 in
76277631
def : Pat<(v4i32 (concat_vectors
76287632
(v2i32 V64:$Vd),
7629-
(v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), (AArch64dup (i64 2147483648))), (i32 32)))))),
7633+
(v2i32 (trunc (AArch64vlshr (add (v2i64 V128:$Vn), VImm0000000080000000), (i32 32)))))),
76307634
(RADDHNv2i64_v4i32
76317635
(INSERT_SUBREG (IMPLICIT_DEF), V64:$Vd, dsub), V128:$Vn,
76327636
(v2i64 (MOVIv2d_ns (i32 0))))>;

‎llvm/test/CodeGen/AArch64/arm64-build-vector.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,8 +120,8 @@ define <2 x double> @poszero_v2f64(<2 x double> %a) {
120120
define <2 x double> @negzero_v2f64(<2 x double> %a) {
121121
; CHECK-LABEL: negzero_v2f64:
122122
; CHECK: // %bb.0:
123-
; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
124-
; CHECK-NEXT: dup v1.2d, x8
123+
; CHECK-NEXT: movi v1.2d, #0000000000000000
124+
; CHECK-NEXT: fneg v1.2d, v1.2d
125125
; CHECK-NEXT: fmul v0.2d, v0.2d, v1.2d
126126
; CHECK-NEXT: ret
127127
%b = fmul <2 x double> %a, <double -0.0, double -0.0>

‎llvm/test/CodeGen/AArch64/fabs-combine.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,8 @@ define <4 x float> @nabsv4f32(<4 x float> %a) {
7171
define <2 x double> @nabsv2d64(<2 x double> %a) {
7272
; CHECK-LABEL: nabsv2d64:
7373
; CHECK: // %bb.0:
74-
; CHECK-NEXT: mov x8, #-9223372036854775808
75-
; CHECK-NEXT: dup v1.2d, x8
74+
; CHECK-NEXT: movi v1.2d, #0000000000000000
75+
; CHECK-NEXT: fneg v1.2d, v1.2d
7676
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
7777
; CHECK-NEXT: ret
7878
%conv = bitcast <2 x double> %a to <2 x i64>

‎llvm/test/CodeGen/AArch64/fcvt_combine.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,8 +110,8 @@ define <2 x i32> @test9(<2 x float> %f) {
110110
define <2 x i32> @test10(<2 x float> %f) {
111111
; CHECK-LABEL: test10:
112112
; CHECK: // %bb.0:
113-
; CHECK-NEXT: mov w8, #2143289344 // =0x7fc00000
114-
; CHECK-NEXT: dup v0.2s, w8
113+
; CHECK-NEXT: mvni v0.2s, #63, msl #16
114+
; CHECK-NEXT: fneg v0.2s, v0.2s
115115
; CHECK-NEXT: fcvtzu v0.2s, v0.2s
116116
; CHECK-NEXT: ret
117117
%mul.i = fmul <2 x float> %f, <float undef, float undef>
@@ -426,8 +426,8 @@ define <2 x i32> @test9_sat(<2 x float> %f) {
426426
define <2 x i32> @test10_sat(<2 x float> %f) {
427427
; CHECK-LABEL: test10_sat:
428428
; CHECK: // %bb.0:
429-
; CHECK-NEXT: mov w8, #2143289344 // =0x7fc00000
430-
; CHECK-NEXT: dup v0.2s, w8
429+
; CHECK-NEXT: mvni v0.2s, #63, msl #16
430+
; CHECK-NEXT: fneg v0.2s, v0.2s
431431
; CHECK-NEXT: fcvtzu v0.2s, v0.2s
432432
; CHECK-NEXT: ret
433433
%mul.i = fmul <2 x float> %f, <float undef, float undef>

‎llvm/test/CodeGen/AArch64/neon-mov.ll‎

Lines changed: 33 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -111,16 +111,14 @@ define <4 x i32> @movi4s_lsl16() {
111111
define <4 x i32> @movi4s_fneg() {
112112
; CHECK-NOFP16-SD-LABEL: movi4s_fneg:
113113
; CHECK-NOFP16-SD: // %bb.0:
114-
; CHECK-NOFP16-SD-NEXT: mov w8, #61440 // =0xf000
115-
; CHECK-NOFP16-SD-NEXT: movk w8, #32768, lsl #16
116-
; CHECK-NOFP16-SD-NEXT: dup v0.4s, w8
114+
; CHECK-NOFP16-SD-NEXT: movi v0.4s, #240, lsl #8
115+
; CHECK-NOFP16-SD-NEXT: fneg v0.4s, v0.4s
117116
; CHECK-NOFP16-SD-NEXT: ret
118117
;
119118
; CHECK-FP16-SD-LABEL: movi4s_fneg:
120119
; CHECK-FP16-SD: // %bb.0:
121-
; CHECK-FP16-SD-NEXT: mov w8, #61440 // =0xf000
122-
; CHECK-FP16-SD-NEXT: movk w8, #32768, lsl #16
123-
; CHECK-FP16-SD-NEXT: dup v0.4s, w8
120+
; CHECK-FP16-SD-NEXT: movi v0.4s, #240, lsl #8
121+
; CHECK-FP16-SD-NEXT: fneg v0.4s, v0.4s
124122
; CHECK-FP16-SD-NEXT: ret
125123
;
126124
; CHECK-NOFP16-GI-LABEL: movi4s_fneg:
@@ -178,11 +176,29 @@ define <8 x i16> @movi8h_lsl8() {
178176
}
179177

180178
define <8 x i16> @movi8h_fneg() {
181-
; CHECK-LABEL: movi8h_fneg:
182-
; CHECK: // %bb.0:
183-
; CHECK-NEXT: adrp x8, .LCPI19_0
184-
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]
185-
; CHECK-NEXT: ret
179+
; CHECK-NOFP16-SD-LABEL: movi8h_fneg:
180+
; CHECK-NOFP16-SD: // %bb.0:
181+
; CHECK-NOFP16-SD-NEXT: movi v0.8h, #127, lsl #8
182+
; CHECK-NOFP16-SD-NEXT: fneg v0.4s, v0.4s
183+
; CHECK-NOFP16-SD-NEXT: ret
184+
;
185+
; CHECK-FP16-SD-LABEL: movi8h_fneg:
186+
; CHECK-FP16-SD: // %bb.0:
187+
; CHECK-FP16-SD-NEXT: movi v0.8h, #127, lsl #8
188+
; CHECK-FP16-SD-NEXT: fneg v0.4s, v0.4s
189+
; CHECK-FP16-SD-NEXT: ret
190+
;
191+
; CHECK-NOFP16-GI-LABEL: movi8h_fneg:
192+
; CHECK-NOFP16-GI: // %bb.0:
193+
; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI19_0
194+
; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]
195+
; CHECK-NOFP16-GI-NEXT: ret
196+
;
197+
; CHECK-FP16-GI-LABEL: movi8h_fneg:
198+
; CHECK-FP16-GI: // %bb.0:
199+
; CHECK-FP16-GI-NEXT: adrp x8, .LCPI19_0
200+
; CHECK-FP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]
201+
; CHECK-FP16-GI-NEXT: ret
186202
ret <8 x i16> <i16 32512, i16 65280, i16 32512, i16 65280, i16 32512, i16 65280, i16 32512, i16 65280>
187203
}
188204

@@ -294,8 +310,8 @@ define <8 x i16> @mvni8h_neg() {
294310
;
295311
; CHECK-FP16-SD-LABEL: mvni8h_neg:
296312
; CHECK-FP16-SD: // %bb.0:
297-
; CHECK-FP16-SD-NEXT: mov w8, #33008 // =0x80f0
298-
; CHECK-FP16-SD-NEXT: dup v0.8h, w8
313+
; CHECK-FP16-SD-NEXT: movi v0.8h, #240
314+
; CHECK-FP16-SD-NEXT: fneg v0.8h, v0.8h
299315
; CHECK-FP16-SD-NEXT: ret
300316
;
301317
; CHECK-NOFP16-GI-LABEL: mvni8h_neg:
@@ -480,14 +496,14 @@ define <2 x double> @fmov2d() {
480496
define <2 x double> @fmov2d_neg0() {
481497
; CHECK-NOFP16-SD-LABEL: fmov2d_neg0:
482498
; CHECK-NOFP16-SD: // %bb.0:
483-
; CHECK-NOFP16-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
484-
; CHECK-NOFP16-SD-NEXT: dup v0.2d, x8
499+
; CHECK-NOFP16-SD-NEXT: movi v0.2d, #0000000000000000
500+
; CHECK-NOFP16-SD-NEXT: fneg v0.2d, v0.2d
485501
; CHECK-NOFP16-SD-NEXT: ret
486502
;
487503
; CHECK-FP16-SD-LABEL: fmov2d_neg0:
488504
; CHECK-FP16-SD: // %bb.0:
489-
; CHECK-FP16-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
490-
; CHECK-FP16-SD-NEXT: dup v0.2d, x8
505+
; CHECK-FP16-SD-NEXT: movi v0.2d, #0000000000000000
506+
; CHECK-FP16-SD-NEXT: fneg v0.2d, v0.2d
491507
; CHECK-FP16-SD-NEXT: ret
492508
;
493509
; CHECK-NOFP16-GI-LABEL: fmov2d_neg0:

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