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AMDGPU: Custom expand flat cmpxchg which may access private
64-bit flat cmpxchg instructions do not work correctly for scratch addresses, and need to be expanded as non-atomic. Allow custom expansion of cmpxchg in AtomicExpand, as is already the case for atomicrmw.
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-164
lines changed

10 files changed

+1157
-164
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2204,6 +2204,11 @@ class TargetLoweringBase {
22042204
"Generic atomicrmw expansion unimplemented on this target");
22052205
}
22062206

2207+
/// Perform a cmpxchg expansion using a target-specific method.
2208+
virtual void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
2209+
llvm_unreachable("Generic cmpxchg expansion unimplemented on this target");
2210+
}
2211+
22072212
/// Perform a bit test atomicrmw using a target-specific intrinsic. This
22082213
/// represents the combined bit test intrinsic which will be lowered at a late
22092214
/// stage by the backend.

‎llvm/include/llvm/Transforms/Utils/LowerAtomic.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,13 @@ class IRBuilderBase;
2323
/// Convert the given Cmpxchg into primitive load and compare.
2424
bool lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI);
2525

26+
/// Emit IR to implement the given cmpxchg operation on values in registers,
27+
/// returning the new value.
28+
std::pair<Value *, Value *> buildAtomicCmpXchgValue(IRBuilderBase &Builder,
29+
Value *Ptr, Value *Cmp,
30+
Value *Val,
31+
Align Alignment);
32+
2633
/// Convert the given RMWI into primitive load and stores,
2734
/// assuming that doing so is legal. Return true if the lowering
2835
/// succeeds.

‎llvm/lib/CodeGen/AtomicExpandPass.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1672,6 +1672,10 @@ bool AtomicExpandImpl::tryExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
16721672
return true;
16731673
case TargetLoweringBase::AtomicExpansionKind::NotAtomic:
16741674
return lowerAtomicCmpXchgInst(CI);
1675+
case TargetLoweringBase::AtomicExpansionKind::Expand: {
1676+
TLI->emitExpandAtomicCmpXchg(CI);
1677+
return true;
1678+
}
16751679
}
16761680
}
16771681

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 95 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -16588,9 +16588,21 @@ SITargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1658816588

1658916589
TargetLowering::AtomicExpansionKind
1659016590
SITargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CmpX) const {
16591-
return CmpX->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS
16592-
? AtomicExpansionKind::NotAtomic
16593-
: AtomicExpansionKind::None;
16591+
unsigned AddrSpace = CmpX->getPointerAddressSpace();
16592+
if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS)
16593+
return AtomicExpansionKind::NotAtomic;
16594+
16595+
if (AddrSpace != AMDGPUAS::FLAT_ADDRESS || !flatInstrMayAccessPrivate(CmpX))
16596+
return AtomicExpansionKind::None;
16597+
16598+
const DataLayout &DL = CmpX->getDataLayout();
16599+
16600+
Type *ValTy = CmpX->getNewValOperand()->getType();
16601+
16602+
// If a 64-bit flat atomic may alias private, we need to avoid using the
16603+
// atomic in the private case.
16604+
return DL.getTypeSizeInBits(ValTy) == 64 ? AtomicExpansionKind::Expand
16605+
: AtomicExpansionKind::None;
1659416606
}
1659516607

1659616608
const TargetRegisterClass *
@@ -16754,40 +16766,8 @@ bool SITargetLowering::checkForPhysRegDependency(
1675416766
return false;
1675516767
}
1675616768

16757-
void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
16758-
AtomicRMWInst::BinOp Op = AI->getOperation();
16759-
16760-
if (Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Or ||
16761-
Op == AtomicRMWInst::Xor) {
16762-
if (auto *ConstVal = dyn_cast<Constant>(AI->getValOperand());
16763-
ConstVal && ConstVal->isNullValue()) {
16764-
// atomicrmw or %ptr, 0 -> atomicrmw add %ptr, 0
16765-
AI->setOperation(AtomicRMWInst::Add);
16766-
16767-
// TODO: Turn the below private handling into a no-op for idempotent
16768-
// cases.
16769-
}
16770-
}
16771-
16772-
// The non-flat expansions should only perform the de-canonicalization of
16773-
// identity values.
16774-
if (AI->getPointerAddressSpace() != AMDGPUAS::FLAT_ADDRESS)
16775-
return;
16776-
16777-
// FullFlatEmulation is true if we need to issue the private, shared, and
16778-
// global cases.
16779-
//
16780-
// If this is false, we are only dealing with the flat-targeting-private case,
16781-
// where we only insert a check for private and still use the flat instruction
16782-
// for global and shared.
16783-
16784-
// TODO: Avoid the private check for the fadd case depending on
16785-
// noalias.addrspace.
16786-
16787-
bool FullFlatEmulation = Op == AtomicRMWInst::FAdd &&
16788-
Subtarget->hasAtomicFaddInsts() &&
16789-
AI->getType()->isFloatTy();
16790-
16769+
void SITargetLowering::emitExpandAtomicAddrSpacePredicate(
16770+
Instruction *AI) const {
1679116771
// Given: atomicrmw fadd ptr %addr, float %val ordering
1679216772
//
1679316773
// With this expansion we produce the following code:
@@ -16834,6 +16814,34 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1683416814
IRBuilder<> Builder(AI);
1683516815
LLVMContext &Ctx = Builder.getContext();
1683616816

16817+
auto *RMW = dyn_cast<AtomicRMWInst>(AI);
16818+
const unsigned PtrOpIdx = RMW ? AtomicRMWInst::getPointerOperandIndex()
16819+
: AtomicCmpXchgInst::getPointerOperandIndex();
16820+
Value *Addr = AI->getOperand(PtrOpIdx);
16821+
16822+
/// TODO: Only need to check private, then emit flat-known-not private (no
16823+
/// need for shared block, or cast to global).
16824+
AtomicCmpXchgInst *CX = dyn_cast<AtomicCmpXchgInst>(AI);
16825+
16826+
Align Alignment;
16827+
if (RMW)
16828+
Alignment = RMW->getAlign();
16829+
else if (CX)
16830+
Alignment = CX->getAlign();
16831+
else
16832+
llvm_unreachable("unhandled atomic operation");
16833+
16834+
// FullFlatEmulation is true if we need to issue the private, shared, and
16835+
// global cases.
16836+
//
16837+
// If this is false, we are only dealing with the flat-targeting-private case,
16838+
// where we only insert a check for private and still use the flat instruction
16839+
// for global and shared.
16840+
16841+
bool FullFlatEmulation = RMW && RMW->getOperation() == AtomicRMWInst::FAdd &&
16842+
Subtarget->hasAtomicFaddInsts() &&
16843+
RMW->getType()->isFloatTy();
16844+
1683716845
// If the return value isn't used, do not introduce a false use in the phi.
1683816846
bool ReturnValueIsUsed = !AI->use_empty();
1683916847

@@ -16855,11 +16863,6 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1685516863
BasicBlock *GlobalBB = BasicBlock::Create(Ctx, "atomicrmw.global", F, ExitBB);
1685616864
BasicBlock *PhiBB = BasicBlock::Create(Ctx, "atomicrmw.phi", F, ExitBB);
1685716865

16858-
Value *Val = AI->getValOperand();
16859-
Type *ValTy = Val->getType();
16860-
Value *Addr = AI->getPointerOperand();
16861-
Align Alignment = AI->getAlign();
16862-
1686316866
std::prev(BB->end())->eraseFromParent();
1686416867
Builder.SetInsertPoint(BB);
1686516868

@@ -16874,8 +16877,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1687416877

1687516878
Instruction *Clone = AI->clone();
1687616879
Clone->insertInto(SharedBB, SharedBB->end());
16877-
Clone->getOperandUse(AtomicRMWInst::getPointerOperandIndex())
16878-
.set(CastToLocal);
16880+
Clone->getOperandUse(PtrOpIdx).set(CastToLocal);
1687916881
LoadedShared = Clone;
1688016882

1688116883
Builder.CreateBr(PhiBB);
@@ -16887,14 +16889,29 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1688716889
Builder.CreateCondBr(IsPrivate, PrivateBB, GlobalBB);
1688816890

1688916891
Builder.SetInsertPoint(PrivateBB);
16892+
1689016893
Value *CastToPrivate = Builder.CreateAddrSpaceCast(
1689116894
Addr, PointerType::get(Ctx, AMDGPUAS::PRIVATE_ADDRESS));
16892-
Value *LoadedPrivate = Builder.CreateAlignedLoad(ValTy, CastToPrivate,
16893-
Alignment, "loaded.private");
1689416895

16895-
Value *NewVal = buildAtomicRMWValue(Op, Builder, LoadedPrivate, Val);
16896+
Value *LoadedPrivate;
16897+
if (RMW) {
16898+
LoadedPrivate = Builder.CreateAlignedLoad(
16899+
RMW->getType(), CastToPrivate, RMW->getAlign(), "loaded.private");
16900+
16901+
Value *NewVal = buildAtomicRMWValue(RMW->getOperation(), Builder,
16902+
LoadedPrivate, RMW->getValOperand());
16903+
16904+
Builder.CreateAlignedStore(NewVal, CastToPrivate, RMW->getAlign());
16905+
} else {
16906+
auto [ResultLoad, Equal] =
16907+
buildAtomicCmpXchgValue(Builder, CastToPrivate, CX->getCompareOperand(),
16908+
CX->getNewValOperand(), CX->getAlign());
16909+
16910+
Value *Insert = Builder.CreateInsertValue(PoisonValue::get(CX->getType()),
16911+
ResultLoad, 0);
16912+
LoadedPrivate = Builder.CreateInsertValue(Insert, Equal, 1);
16913+
}
1689616914

16897-
Builder.CreateAlignedStore(NewVal, CastToPrivate, Alignment);
1689816915
Builder.CreateBr(PhiBB);
1689916916

1690016917
Builder.SetInsertPoint(GlobalBB);
@@ -16904,8 +16921,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1690416921
if (FullFlatEmulation) {
1690516922
Value *CastToGlobal = Builder.CreateAddrSpaceCast(
1690616923
Addr, PointerType::get(Ctx, AMDGPUAS::GLOBAL_ADDRESS));
16907-
AI->getOperandUse(AtomicRMWInst::getPointerOperandIndex())
16908-
.set(CastToGlobal);
16924+
AI->getOperandUse(PtrOpIdx).set(CastToGlobal);
1690916925
}
1691016926

1691116927
AI->removeFromParent();
@@ -16929,7 +16945,7 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1692916945
Builder.SetInsertPoint(PhiBB);
1693016946

1693116947
if (ReturnValueIsUsed) {
16932-
PHINode *Loaded = Builder.CreatePHI(ValTy, 3);
16948+
PHINode *Loaded = Builder.CreatePHI(AI->getType(), 3);
1693316949
AI->replaceAllUsesWith(Loaded);
1693416950
if (FullFlatEmulation)
1693516951
Loaded->addIncoming(LoadedShared, SharedBB);
@@ -16941,6 +16957,34 @@ void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
1694116957
Builder.CreateBr(ExitBB);
1694216958
}
1694316959

16960+
void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
16961+
AtomicRMWInst::BinOp Op = AI->getOperation();
16962+
16963+
if (Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Or ||
16964+
Op == AtomicRMWInst::Xor) {
16965+
if (const auto *ConstVal = dyn_cast<Constant>(AI->getValOperand());
16966+
ConstVal && ConstVal->isNullValue()) {
16967+
// atomicrmw or %ptr, 0 -> atomicrmw add %ptr, 0
16968+
AI->setOperation(AtomicRMWInst::Add);
16969+
16970+
// We may still need the private-alias-flat handling below.
16971+
16972+
// TODO: Skip this for cases where we cannot access remote memory.
16973+
}
16974+
}
16975+
16976+
// The non-flat expansions should only perform the de-canonicalization of
16977+
// identity values.
16978+
if (AI->getPointerAddressSpace() != AMDGPUAS::FLAT_ADDRESS)
16979+
return;
16980+
16981+
emitExpandAtomicAddrSpacePredicate(AI);
16982+
}
16983+
16984+
void SITargetLowering::emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const {
16985+
emitExpandAtomicAddrSpacePredicate(CI);
16986+
}
16987+
1694416988
LoadInst *
1694516989
SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
1694616990
IRBuilder<> Builder(AI);

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -544,7 +544,10 @@ class SITargetLowering final : public AMDGPUTargetLowering {
544544
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
545545
AtomicExpansionKind
546546
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
547+
548+
void emitExpandAtomicAddrSpacePredicate(Instruction *AI) const;
547549
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
550+
void emitExpandAtomicCmpXchg(AtomicCmpXchgInst *CI) const override;
548551

549552
LoadInst *
550553
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;

‎llvm/lib/Transforms/Utils/LowerAtomic.cpp

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,20 +25,29 @@ bool llvm::lowerAtomicCmpXchgInst(AtomicCmpXchgInst *CXI) {
2525
Value *Cmp = CXI->getCompareOperand();
2626
Value *Val = CXI->getNewValOperand();
2727

28-
LoadInst *Orig =
29-
Builder.CreateAlignedLoad(Val->getType(), Ptr, CXI->getAlign());
30-
Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
31-
Value *Res = Builder.CreateSelect(Equal, Val, Orig);
32-
Builder.CreateAlignedStore(Res, Ptr, CXI->getAlign());
28+
auto [Orig, Equal] =
29+
buildAtomicCmpXchgValue(Builder, Ptr, Cmp, Val, CXI->getAlign());
3330

34-
Res = Builder.CreateInsertValue(PoisonValue::get(CXI->getType()), Orig, 0);
31+
Value *Res =
32+
Builder.CreateInsertValue(PoisonValue::get(CXI->getType()), Orig, 0);
3533
Res = Builder.CreateInsertValue(Res, Equal, 1);
3634

3735
CXI->replaceAllUsesWith(Res);
3836
CXI->eraseFromParent();
3937
return true;
4038
}
4139

40+
std::pair<Value *, Value *>
41+
llvm::buildAtomicCmpXchgValue(IRBuilderBase &Builder, Value *Ptr, Value *Cmp,
42+
Value *Val, Align Alignment) {
43+
LoadInst *Orig = Builder.CreateAlignedLoad(Val->getType(), Ptr, Alignment);
44+
Value *Equal = Builder.CreateICmpEQ(Orig, Cmp);
45+
Value *Res = Builder.CreateSelect(Equal, Val, Orig);
46+
Builder.CreateAlignedStore(Res, Ptr, Alignment);
47+
48+
return {Orig, Equal};
49+
}
50+
4251
Value *llvm::buildAtomicRMWValue(AtomicRMWInst::BinOp Op,
4352
IRBuilderBase &Builder, Value *Loaded,
4453
Value *Val) {

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