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lukel97lukel97
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[RISCV] Fold vmv.x.s into load from stack (#109774)
If a vector is reloaded from the stack to be used in vmv.x.s, we can tell foldMemoryOperandImpl to fold it into a scalar load. If XLEN < SEW then this currently just bails. I couldn't think of a way to express a vmv.x.s that truncates in LLVM IR.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

+23
Original file line numberDiff line numberDiff line change
@@ -761,6 +761,29 @@ MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
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LoadOpc = RISCV::LBU;
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break;
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}
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if (RISCV::getRVVMCOpcode(MI.getOpcode()) == RISCV::VMV_X_S) {
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unsigned Log2SEW =
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MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
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if (STI.getXLen() < (1 << Log2SEW))
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return nullptr;
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switch (Log2SEW) {
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case 3:
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LoadOpc = RISCV::LB;
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break;
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case 4:
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LoadOpc = RISCV::LH;
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break;
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case 5:
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LoadOpc = RISCV::LW;
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break;
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case 6:
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LoadOpc = RISCV::LD;
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break;
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default:
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llvm_unreachable("Unexpected SEW");
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}
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break;
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}
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return nullptr;
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case RISCV::SEXT_H:
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LoadOpc = RISCV::LH;

‎llvm/test/CodeGen/RISCV/rvv/stack-folding.ll

+162
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV32 %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck --check-prefixes=CHECK,RV64 %s
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define i64 @i64(<vscale x 1 x i64> %v, i1 %c) {
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; RV32-LABEL: i64:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: .cfi_def_cfa_offset 16
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; RV32-NEXT: csrr a1, vlenb
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; RV32-NEXT: slli a1, a1, 1
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; RV32-NEXT: sub sp, sp, a1
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; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
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; RV32-NEXT: addi a1, sp, 16
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; RV32-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: #APP
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; RV32-NEXT: #NO_APP
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; RV32-NEXT: beqz a0, .LBB0_2
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; RV32-NEXT: # %bb.1: # %truebb
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
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; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV32-NEXT: vsrl.vx v8, v9, a0
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; RV32-NEXT: vmv.x.s a1, v8
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; RV32-NEXT: vmv.x.s a0, v9
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; RV32-NEXT: j .LBB0_3
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; RV32-NEXT: .LBB0_2: # %falsebb
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: .LBB0_3: # %falsebb
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; RV32-NEXT: csrr a2, vlenb
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; RV32-NEXT: slli a2, a2, 1
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; RV32-NEXT: add sp, sp, a2
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: i64:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: .cfi_def_cfa_offset 16
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; RV64-NEXT: csrr a1, vlenb
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; RV64-NEXT: slli a1, a1, 1
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; RV64-NEXT: sub sp, sp, a1
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; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
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; RV64-NEXT: addi a1, sp, 16
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; RV64-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: #APP
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; RV64-NEXT: #NO_APP
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; RV64-NEXT: beqz a0, .LBB0_2
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; RV64-NEXT: # %bb.1: # %truebb
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; RV64-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
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; RV64-NEXT: .LBB0_2: # %falsebb
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; RV64-NEXT: csrr a1, vlenb
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; RV64-NEXT: slli a1, a1, 1
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; RV64-NEXT: add sp, sp, a1
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
60+
br i1 %c, label %truebb, label %falsebb
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truebb:
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%x = extractelement <vscale x 1 x i64> %v, i32 0
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ret i64 %x
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falsebb:
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ret i64 0
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}
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define i32 @i32(<vscale x 2 x i32> %v, i1 %c) {
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; CHECK-LABEL: i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: beqz a0, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %truebb
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; CHECK-NEXT: lw a0, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: .LBB1_2: # %falsebb
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: add sp, sp, a1
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
92+
br i1 %c, label %truebb, label %falsebb
93+
truebb:
94+
%x = extractelement <vscale x 2 x i32> %v, i32 0
95+
ret i32 %x
96+
falsebb:
97+
ret i32 0
98+
}
99+
100+
define i16 @i16(<vscale x 4 x i16> %v, i1 %c) {
101+
; CHECK-LABEL: i16:
102+
; CHECK: # %bb.0:
103+
; CHECK-NEXT: addi sp, sp, -16
104+
; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: beqz a0, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %truebb
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; CHECK-NEXT: lh a0, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: .LBB2_2: # %falsebb
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: add sp, sp, a1
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
124+
br i1 %c, label %truebb, label %falsebb
125+
truebb:
126+
%x = extractelement <vscale x 4 x i16> %v, i32 0
127+
ret i16 %x
128+
falsebb:
129+
ret i16 0
130+
}
131+
132+
define i8 @i8(<vscale x 8 x i8> %v, i1 %c) {
133+
; CHECK-LABEL: i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
141+
; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: beqz a0, .LBB3_2
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; CHECK-NEXT: # %bb.1: # %truebb
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; CHECK-NEXT: lb a0, 16(sp) # 8-byte Folded Reload
149+
; CHECK-NEXT: .LBB3_2: # %falsebb
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: add sp, sp, a1
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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tail call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
156+
br i1 %c, label %truebb, label %falsebb
157+
truebb:
158+
%x = extractelement <vscale x 8 x i8> %v, i32 0
159+
ret i8 %x
160+
falsebb:
161+
ret i8 0
162+
}

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