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[LV] Handle SwitchInst in ::isPredicatedInst.
After f0df4fb, isPredicatedInst needs to handle SwitchInst as well. Handle it the same as BranchInst. This fixes a crash in the newly added test and improves the results for one of the existing tests in predicate-switch.ll Should fix https://lab.llvm.org/buildbot/#/builders/113/builds/2099.
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-3
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3 files changed

+154
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‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3343,7 +3343,7 @@ bool LoopVectorizationCostModel::isPredicatedInst(Instruction *I) const {
33433343
if (!blockNeedsPredicationForAnyReason(I->getParent()) ||
33443344
isSafeToSpeculativelyExecute(I) ||
33453345
(isa<LoadInst, StoreInst, CallInst>(I) && !Legal->isMaskRequired(I)) ||
3346-
isa<BranchInst, PHINode, AllocaInst>(I))
3346+
isa<BranchInst, SwitchInst, PHINode, AllocaInst>(I))
33473347
return false;
33483348

33493349
// If the instruction was executed conditionally in the original scalar loop,

‎llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll

Lines changed: 47 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -964,9 +964,52 @@ define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end,
964964
; COST-LABEL: define void @switch_under_br_default_common_dest_with_case(
965965
; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {
966966
; COST-NEXT: [[ENTRY:.*]]:
967+
; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
968+
; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
969+
; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
970+
; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
971+
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
972+
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
973+
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
974+
; COST-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
975+
; COST: [[VECTOR_PH]]:
976+
; COST-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 4
977+
; COST-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
978+
; COST-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 8
979+
; COST-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
980+
; COST-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[X]], i64 0
981+
; COST-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
982+
; COST-NEXT: br label %[[VECTOR_BODY:.*]]
983+
; COST: [[VECTOR_BODY]]:
984+
; COST-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
985+
; COST-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 8
986+
; COST-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
987+
; COST-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]]
988+
; COST-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[NEXT_GEP]], i32 0
989+
; COST-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP6]], align 1
990+
; COST-NEXT: [[TMP7:%.*]] = icmp ule <4 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
991+
; COST-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], <i64 -12, i64 -12, i64 -12, i64 -12>
992+
; COST-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], <i64 13, i64 13, i64 13, i64 13>
993+
; COST-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP8]], <4 x i1> zeroinitializer
994+
; COST-NEXT: [[TMP11:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP9]], <4 x i1> zeroinitializer
995+
; COST-NEXT: [[TMP12:%.*]] = or <4 x i1> [[TMP10]], [[TMP11]]
996+
; COST-NEXT: [[TMP13:%.*]] = xor <4 x i1> [[TMP12]], <i1 true, i1 true, i1 true, i1 true>
997+
; COST-NEXT: [[TMP14:%.*]] = select <4 x i1> [[TMP7]], <4 x i1> [[TMP13]], <4 x i1> zeroinitializer
998+
; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr [[TMP6]], i32 1, <4 x i1> [[TMP11]])
999+
; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> <i64 42, i64 42, i64 42, i64 42>, ptr [[TMP6]], i32 1, <4 x i1> [[TMP10]])
1000+
; COST-NEXT: [[TMP15:%.*]] = or <4 x i1> [[TMP14]], [[TMP14]]
1001+
; COST-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> <i64 2, i64 2, i64 2, i64 2>, ptr [[TMP6]], i32 1, <4 x i1> [[TMP15]])
1002+
; COST-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
1003+
; COST-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
1004+
; COST-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
1005+
; COST: [[MIDDLE_BLOCK]]:
1006+
; COST-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
1007+
; COST-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
1008+
; COST: [[SCALAR_PH]]:
1009+
; COST-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
9671010
; COST-NEXT: br label %[[LOOP_HEADER:.*]]
9681011
; COST: [[LOOP_HEADER]]:
969-
; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[START]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
1012+
; COST-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
9701013
; COST-NEXT: [[L:%.*]] = load i64, ptr [[PTR_IV]], align 1
9711014
; COST-NEXT: [[C:%.*]] = icmp ule i64 [[L]], [[X]]
9721015
; COST-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
@@ -988,7 +1031,7 @@ define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end,
9881031
; COST: [[LOOP_LATCH]]:
9891032
; COST-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i64, ptr [[PTR_IV]], i64 1
9901033
; COST-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV_NEXT]], [[END]]
991-
; COST-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
1034+
; COST-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]]
9921035
; COST: [[EXIT]]:
9931036
; COST-NEXT: ret void
9941037
;
@@ -1464,6 +1507,8 @@ exit:
14641507
; COST: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
14651508
; COST: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
14661509
; COST: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
1510+
; COST: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
1511+
; COST: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
14671512
;.
14681513
; FORCED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
14691514
; FORCED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}

‎llvm/test/Transforms/LoopVectorize/tail-folding-switch.ll

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,106 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -prefer-predicate-over-epilogue=predicate-dont-vectorize -S %s | FileCheck %s
3+
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
4+
5+
define void @tail_fold_switch(ptr %dst, i32 %0) {
6+
; CHECK-LABEL: define void @tail_fold_switch(
7+
; CHECK-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {
8+
; CHECK-NEXT: [[ENTRY:.*]]:
9+
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
10+
; CHECK: [[VECTOR_PH]]:
11+
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
12+
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
13+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
14+
; CHECK: [[VECTOR_BODY]]:
15+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
16+
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
17+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
18+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], <i32 1, i32 1, i32 1, i32 1>
19+
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP2]], <4 x i1> zeroinitializer
20+
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP3]], i32 0
21+
; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
22+
; CHECK: [[PRED_STORE_IF]]:
23+
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0
24+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP5]]
25+
; CHECK-NEXT: store i32 0, ptr [[TMP6]], align 4
26+
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
27+
; CHECK: [[PRED_STORE_CONTINUE]]:
28+
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP3]], i32 1
29+
; CHECK-NEXT: br i1 [[TMP7]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
30+
; CHECK: [[PRED_STORE_IF1]]:
31+
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1
32+
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP8]]
33+
; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 4
34+
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
35+
; CHECK: [[PRED_STORE_CONTINUE2]]:
36+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP3]], i32 2
37+
; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
38+
; CHECK: [[PRED_STORE_IF3]]:
39+
; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 2
40+
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP11]]
41+
; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 4
42+
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
43+
; CHECK: [[PRED_STORE_CONTINUE4]]:
44+
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP3]], i32 3
45+
; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
46+
; CHECK: [[PRED_STORE_IF5]]:
47+
; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 3
48+
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP14]]
49+
; CHECK-NEXT: store i32 0, ptr [[TMP15]], align 4
50+
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
51+
; CHECK: [[PRED_STORE_CONTINUE6]]:
52+
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
53+
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
54+
; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8
55+
; CHECK-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
56+
; CHECK: [[MIDDLE_BLOCK]]:
57+
; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
58+
; CHECK: [[SCALAR_PH]]:
59+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 8, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
60+
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
61+
; CHECK: [[LOOP_HEADER]]:
62+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
63+
; CHECK-NEXT: switch i32 [[TMP0]], label %[[LOOP_LATCH]] [
64+
; CHECK-NEXT: i32 0, label %[[LOOP_LATCH]]
65+
; CHECK-NEXT: i32 1, label %[[IF_THEN:.*]]
66+
; CHECK-NEXT: ]
67+
; CHECK: [[IF_THEN]]:
68+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[IV]]
69+
; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
70+
; CHECK-NEXT: br label %[[LOOP_LATCH]]
71+
; CHECK: [[LOOP_LATCH]]:
72+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
73+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 4
74+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
75+
; CHECK: [[EXIT]]:
76+
; CHECK-NEXT: ret void
77+
;
78+
entry:
79+
br label %loop.header
80+
81+
loop.header:
82+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
83+
switch i32 %0, label %loop.latch [
84+
i32 0, label %loop.latch
85+
i32 1, label %if.then
86+
]
87+
88+
if.then:
89+
%gep = getelementptr inbounds i32, ptr %dst, i64 %iv
90+
store i32 0, ptr %gep, align 4
91+
br label %loop.latch
92+
93+
loop.latch:
94+
%iv.next = add i64 %iv, 1
95+
%ec = icmp eq i64 %iv, 4
96+
br i1 %ec, label %exit, label %loop.header
97+
98+
exit:
99+
ret void
100+
}
101+
;.
102+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
103+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
104+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
105+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
106+
;.

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