fix comments

Author: shiltian

llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

@@ -1356,19 +1356,21 @@ struct AAAMDGPUUniformArgument : public AAAMDGPUUniform {
 
   ChangeStatus updateImpl(Attributor &A) override {
     unsigned ArgNo = getAssociatedArgument()->getArgNo();
-    TargetMachine &TM =
-        static_cast<AMDGPUInformationCache &>(A.getInfoCache()).TM;
 
     auto isUniform = [&](AbstractCallSite ACS) -> bool {
       CallBase *CB = ACS.getInstruction();
       Value *V = CB->getArgOperand(ArgNo);
+      if (isa<Constant>(V))
+        return true;
       if (auto *Arg = dyn_cast<Argument>(V)) {
         auto *AA = A.getOrCreateAAFor<AAAMDGPUUniform>(
             IRPosition::argument(*Arg), this, DepClassTy::REQUIRED);
         return AA && AA->isValidState();
       }
-      TargetTransformInfo TTI = TM.getTargetTransformInfo(*CB->getFunction());
-      return TTI.isAlwaysUniform(V);
+      TargetTransformInfo *TTI =
+          A.getInfoCache().getAnalysisResultForFunction<TargetIRAnalysis>(
+              *CB->getFunction());
+      return TTI->isAlwaysUniform(V);
     };
 
     bool UsedAssumedInformation = true;

llvm/test/CodeGen/AMDGPU/aa-inreg-inference.ll

@@ -4,21 +4,20 @@
 @g1 = protected addrspace(1) externally_initialized global i32 0, align 4
 @g2 = protected addrspace(1) externally_initialized global i32 0, align 4
 @g3 = protected addrspace(1) externally_initialized global i32 0, align 4
-@g4 = protected addrspace(1) externally_initialized global i32 0, align 4
 
 define internal void @callee_with_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
 ; CHECK-LABEL: define internal void @callee_with_always_uniform_argument(
 ; CHECK-SAME: ptr addrspace(1) inreg [[X:%.*]], i32 inreg [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
-; CHECK-NEXT:    store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
-; CHECK-NEXT:    store i32 [[Y]], ptr addrspace(1) @g4, align 4
+; CHECK-NEXT:    store i32 [[X_VAL]], ptr addrspace(1) @g2, align 4
+; CHECK-NEXT:    store i32 [[Y]], ptr addrspace(1) @g3, align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %x.val = load i32, ptr addrspace(1) %x, align 4
-  store i32 %x.val, ptr addrspace(1) @g3, align 4
-  store i32 %y, ptr addrspace(1) @g4, align 4
+  store i32 %x.val, ptr addrspace(1) @g2, align 4
+  store i32 %y, ptr addrspace(1) @g3, align 4
   ret void
 }
 
@@ -36,19 +35,31 @@ entry:
   ret void
 }
 
+define amdgpu_kernel void @kernel_with_constant(i32 %x) {
+; CHECK-LABEL: define amdgpu_kernel void @kernel_with_constant(
+; CHECK-SAME: i32 [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    call void @callee_with_always_uniform_argument(ptr addrspace(1) @g1, i32 [[X]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  call void @callee_with_always_uniform_argument(ptr addrspace(1) @g1, i32 %x)
+  ret void
+}
+
 define internal void @callee_without_always_uniform_argument(ptr addrspace(1) %x, i32 %y) {
 ; CHECK-LABEL: define internal void @callee_without_always_uniform_argument(
 ; CHECK-SAME: ptr addrspace(1) [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
 ; CHECK-NEXT:    [[X_VAL:%.*]] = load i32, ptr addrspace(1) [[X]], align 4
-; CHECK-NEXT:    store i32 [[X_VAL]], ptr addrspace(1) @g3, align 4
-; CHECK-NEXT:    store i32 [[Y]], ptr addrspace(1) @g4, align 4
+; CHECK-NEXT:    store i32 [[X_VAL]], ptr addrspace(1) @g2, align 4
+; CHECK-NEXT:    store i32 [[Y]], ptr addrspace(1) @g3, align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %x.val = load i32, ptr addrspace(1) %x, align 4
-  store i32 %x.val, ptr addrspace(1) @g3, align 4
-  store i32 %y, ptr addrspace(1) @g4, align 4
+  store i32 %x.val, ptr addrspace(1) @g2, align 4
+  store i32 %y, ptr addrspace(1) @g3, align 4
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/attributor-noalias-addrspace.ll

@@ -480,7 +480,7 @@ bb.2.end:
 
 define internal void @callee_no_alias_addr_space_select(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {
 ; CHECK-LABEL: define internal void @callee_no_alias_addr_space_select(
-; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {
+; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 inreg [[COND1:%.*]], i1 inreg [[COND2:%.*]], i32 inreg [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {
 ; CHECK-NEXT:    [[PTR4:%.*]] = select i1 [[COND1]], ptr addrspacecast (ptr addrspace(1) @gptr to ptr), ptr addrspacecast (ptr addrspace(4) @gptr2 to ptr)
 ; CHECK-NEXT:    [[PTR5:%.*]] = select i1 [[COND2]], ptr [[PTR4]], ptr addrspacecast (ptr addrspace(3) @gptr3 to ptr)
 ; CHECK-NEXT:    store i32 [[VAL]], ptr [[PTR5]], align 4, !noalias.addrspace [[META1:![0-9]+]]
@@ -516,7 +516,7 @@ define internal void @callee_no_alias_addr_space_select(ptr %ptr1, ptr %ptr2, pt
 
 define internal void @callee_alias_addr_space_branch(ptr %ptr1, ptr %ptr2, ptr %ptr3, i1 %cond1, i1 %cond2, i32 %val) #0 {
 ; CHECK-LABEL: define internal void @callee_alias_addr_space_branch(
-; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]]) #[[ATTR1]] {
+; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]], ptr [[PTR3:%.*]], i1 inreg [[COND1:%.*]], i1 inreg [[COND2:%.*]], i32 inreg [[VAL:%.*]]) #[[ATTR1]] {
 ; CHECK-NEXT:    br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]
 ; CHECK:       [[BB_1_TRUE]]:
 ; CHECK-NEXT:    br label %[[BB_1_END:.*]]