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[RISCV] Add Syntacore SCR5 RV32/64 processors definition
Syntacore SCR5 is an entry-level Linux-capable 32/64-bit RISC-V processor core. Overview: https://syntacore.com/products/scr5 Co-authored-by: Dmitrii Petrov <[email protected]> Co-authored-by: Anton Afanasyev <[email protected]>
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‎clang/test/Driver/riscv-cpus.c

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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr4-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR4-RV64 %s
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// MTUNE-SYNTACORE-SCR4-RV64: "-tune-cpu" "syntacore-scr4-rv64"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV32 %s
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// MCPU-SYNTACORE-SCR5-RV32: "-target-cpu" "syntacore-scr5-rv32"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+m"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+a"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+f"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+d"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+c"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zicsr"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-feature" "+zifencei"
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// MCPU-SYNTACORE-SCR5-RV32-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr5-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV32 %s
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// MTUNE-SYNTACORE-SCR5-RV32: "-tune-cpu" "syntacore-scr5-rv32"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr5-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR5-RV64 %s
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// MCPU-SYNTACORE-SCR5-RV64: "-target-cpu" "syntacore-scr5-rv64"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+m"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+a"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+f"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+d"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+c"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zicsr"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-feature" "+zifencei"
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// MCPU-SYNTACORE-SCR5-RV64-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
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// MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"

‎clang/test/Misc/target-invalid-cpu-note.c

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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32{{$}}
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// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, syntacore-scr5-rv32{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, syntacore-scr5-rv64, veyron-v1, xiangshan-nanhu{{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, syntacore-scr4-rv32, syntacore-scr5-rv32, generic, rocket, sifive-7-series{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, syntacore-scr5-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

‎llvm/docs/ReleaseNotes.rst

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* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
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* Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
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FeatureStdExtC],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,
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[Feature64Bit,

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