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1 parent 7edc140 commit 48935fdCopy full SHA for 48935fd
llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
@@ -881,6 +881,7 @@ body: |
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# GCN: %6:vgpr_32 = V_ADD_I16_e64 4, %5, 0, %1, 0, 0, implicit $exec
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# GCN: %8:vgpr_32 = V_ADD_I16_e64 0, %7, 4, %1, 0, 0, implicit $exec
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# GCN: %10:vgpr_32 = V_ADD_I16_e64 4, %9, 4, %1, 0, 0, implicit $exec
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+# GCN: %12:vgpr_32 = V_ADD_I16_e64 8, %11, 0, %1, 0, 0, implicit $exec
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name: opsel_vop3
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tracksRegLiveness: true
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body: |
@@ -906,6 +907,10 @@ body: |
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; Do not combine for op_sel:[1,1,0]
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%9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
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%10:vgpr_32 = V_ADD_I16_e64 4, %9, 4, %1, 0, 0, implicit $exec
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+
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+ ; Do not combine for op_sel:[0,0,1] (dst_op_sel only)
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+ %11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
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+ %12:vgpr_32 = V_ADD_I16_e64 8, %11, 0, %1, 0, 0, implicit $exec
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...
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# Check op_sel is all 0s and op_sel_hi is all 1s when combining
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