add AddPromotedToType(ISD::FMA, MVT::f16, MVT::f64);

Author: folkertdev

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

@@ -3518,7 +3518,8 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FMAD(SDNode *N) {
 
   SDValue Res;
   if (OVT == MVT::f16) {
-    // An f16 fma must go via f64 to prevent double rounding issues.
+    // If f16 fma is not natively supported, the value must be promoted to an
+    // f64 (and not to f32!) to prevent double rounding issues.
     SDValue A64 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Op0, Flags);
     SDValue B64 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Op1, Flags);
     SDValue C64 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Op2, Flags);

llvm/lib/CodeGen/TargetLoweringBase.cpp

@@ -842,6 +842,11 @@ void TargetLoweringBase::initActions() {
     }
   }
 
+  // If f16 fma is not natively supported, the value must be promoted to an f64
+  // (and not to f32!) to prevent double rounding issues.
+  AddPromotedToType(ISD::FMA, MVT::f16, MVT::f64);
+  AddPromotedToType(ISD::STRICT_FMA, MVT::f16, MVT::f64);
+
   // Set default actions for various operations.
   for (MVT VT : MVT::all_valuetypes()) {
     // Default all indexed load / store to expand.

llvm/test/CodeGen/AArch64/f16-instructions.ll

@@ -1378,11 +1378,11 @@ define half @test_log2(half %a) #0 {
 define half @test_fma(half %a, half %b, half %c) #0 {
 ; CHECK-CVT-SD-LABEL: test_fma:
 ; CHECK-CVT-SD:       // %bb.0:
-; CHECK-CVT-SD-NEXT:    fcvt s2, h2
-; CHECK-CVT-SD-NEXT:    fcvt s1, h1
-; CHECK-CVT-SD-NEXT:    fcvt s0, h0
-; CHECK-CVT-SD-NEXT:    fmadd s0, s0, s1, s2
-; CHECK-CVT-SD-NEXT:    fcvt h0, s0
+; CHECK-CVT-SD-NEXT:    fcvt d2, h2
+; CHECK-CVT-SD-NEXT:    fcvt d1, h1
+; CHECK-CVT-SD-NEXT:    fcvt d0, h0
+; CHECK-CVT-SD-NEXT:    fmadd d0, d0, d1, d2
+; CHECK-CVT-SD-NEXT:    fcvt h0, d0
 ; CHECK-CVT-SD-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: test_fma: