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[AArch64][GlobalISel] Add a number of ptr shufflevector tests. NFC
1 parent d7263d6 commit 42da815

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6 files changed

+239
-58
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6 files changed

+239
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lines changed

‎llvm/test/CodeGen/AArch64/arm64-ext.ll

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
22
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
3+
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for test_v2p0
46

57
define <8 x i8> @test_vextd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
68
; CHECK-LABEL: test_vextd:
@@ -131,3 +133,12 @@ define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
131133
%s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
132134
ret <2 x i64> %s
133135
}
136+
137+
define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
138+
; CHECK-LABEL: test_v2p0:
139+
; CHECK: // %bb.0:
140+
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
141+
; CHECK-NEXT: ret
142+
%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
143+
ret <2 x ptr> %s
144+
}

‎llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll

Lines changed: 55 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,51 +1,90 @@
1-
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-GI
24

35
; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
46

57
define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
6-
; CHECK: v8i8
7-
; CHECK: ext.16b v0, v0, v0, #8
8-
; CHECK: ret
8+
; CHECK-LABEL: v8i8:
9+
; CHECK: // %bb.0:
10+
; CHECK-NEXT: ext.16b v0, v0, v0, #8
11+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
12+
; CHECK-NEXT: ret
913
%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1014
ret <8 x i8> %ret
1115
}
1216

1317
define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
1418
; CHECK-LABEL: v4i16:
15-
; CHECK: ext.16b v0, v0, v0, #8
16-
; CHECK: ret
19+
; CHECK: // %bb.0:
20+
; CHECK-NEXT: ext.16b v0, v0, v0, #8
21+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
22+
; CHECK-NEXT: ret
1723
%ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
1824
ret <4 x i16> %ret
1925
}
2026

2127
define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
2228
; CHECK-LABEL: v2i32:
23-
; CHECK: ext.16b v0, v0, v0, #8
24-
; CHECK: ret
29+
; CHECK: // %bb.0:
30+
; CHECK-NEXT: ext.16b v0, v0, v0, #8
31+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
32+
; CHECK-NEXT: ret
2533
%ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
2634
ret <2 x i32> %ret
2735
}
2836

2937
define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
30-
; CHECK-LABEL: v1i64:
31-
; CHECK: ext.16b v0, v0, v0, #8
32-
; CHECK: ret
38+
; CHECK-SD-LABEL: v1i64:
39+
; CHECK-SD: // %bb.0:
40+
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
41+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
42+
; CHECK-SD-NEXT: ret
43+
;
44+
; CHECK-GI-LABEL: v1i64:
45+
; CHECK-GI: // %bb.0:
46+
; CHECK-GI-NEXT: mov d0, v0[1]
47+
; CHECK-GI-NEXT: ret
3348
%ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
3449
ret <1 x i64> %ret
3550
}
3651

52+
define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
53+
; CHECK-SD-LABEL: v1p0:
54+
; CHECK-SD: // %bb.0:
55+
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
56+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
57+
; CHECK-SD-NEXT: ret
58+
;
59+
; CHECK-GI-LABEL: v1p0:
60+
; CHECK-GI: // %bb.0:
61+
; CHECK-GI-NEXT: mov d0, v0[1]
62+
; CHECK-GI-NEXT: ret
63+
%ret = shufflevector <2 x ptr> %a, <2 x ptr> %a, <1 x i32> <i32 1>
64+
ret <1 x ptr> %ret
65+
}
66+
3767
define <2 x float> @v2f32(<4 x float> %a) nounwind {
3868
; CHECK-LABEL: v2f32:
39-
; CHECK: ext.16b v0, v0, v0, #8
40-
; CHECK: ret
69+
; CHECK: // %bb.0:
70+
; CHECK-NEXT: ext.16b v0, v0, v0, #8
71+
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
72+
; CHECK-NEXT: ret
4173
%ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
4274
ret <2 x float> %ret
4375
}
4476

4577
define <1 x double> @v1f64(<2 x double> %a) nounwind {
46-
; CHECK-LABEL: v1f64:
47-
; CHECK: ext.16b v0, v0, v0, #8
48-
; CHECK: ret
78+
; CHECK-SD-LABEL: v1f64:
79+
; CHECK-SD: // %bb.0:
80+
; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
81+
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
82+
; CHECK-SD-NEXT: ret
83+
;
84+
; CHECK-GI-LABEL: v1f64:
85+
; CHECK-GI: // %bb.0:
86+
; CHECK-GI-NEXT: mov d0, v0[1]
87+
; CHECK-GI-NEXT: ret
4988
%ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
5089
ret <1 x double> %ret
5190
}

‎llvm/test/CodeGen/AArch64/neon-perm.ll

Lines changed: 68 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,13 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3-
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for test_vuzp1q_p0
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vuzp2q_p0
7+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vzip1q_p0
8+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vzip2q_p0
9+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vtrn1q_p0
10+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_vtrn2q_p0
411

512
%struct.int8x8x2_t = type { [2 x <8 x i8>] }
613
%struct.int16x4x2_t = type { [2 x <4 x i16>] }
@@ -161,6 +168,16 @@ entry:
161168
ret <2 x i64> %shuffle.i
162169
}
163170

171+
define <2 x ptr> @test_vuzp1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
172+
; CHECK-LABEL: test_vuzp1q_p0:
173+
; CHECK: // %bb.0: // %entry
174+
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
175+
; CHECK-NEXT: ret
176+
entry:
177+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
178+
ret <2 x ptr> %shuffle.i
179+
}
180+
164181
define <2 x float> @test_vuzp1_f32(<2 x float> %a, <2 x float> %b) {
165182
; CHECK-LABEL: test_vuzp1_f32:
166183
; CHECK: // %bb.0: // %entry
@@ -371,6 +388,16 @@ entry:
371388
ret <2 x i64> %shuffle.i
372389
}
373390

391+
define <2 x ptr> @test_vuzp2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
392+
; CHECK-LABEL: test_vuzp2q_p0:
393+
; CHECK: // %bb.0: // %entry
394+
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
395+
; CHECK-NEXT: ret
396+
entry:
397+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
398+
ret <2 x ptr> %shuffle.i
399+
}
400+
374401
define <2 x float> @test_vuzp2_f32(<2 x float> %a, <2 x float> %b) {
375402
; CHECK-LABEL: test_vuzp2_f32:
376403
; CHECK: // %bb.0: // %entry
@@ -581,6 +608,16 @@ entry:
581608
ret <2 x i64> %shuffle.i
582609
}
583610

611+
define <2 x ptr> @test_vzip1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
612+
; CHECK-LABEL: test_vzip1q_p0:
613+
; CHECK: // %bb.0: // %entry
614+
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
615+
; CHECK-NEXT: ret
616+
entry:
617+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
618+
ret <2 x ptr> %shuffle.i
619+
}
620+
584621
define <2 x float> @test_vzip1_f32(<2 x float> %a, <2 x float> %b) {
585622
; CHECK-LABEL: test_vzip1_f32:
586623
; CHECK: // %bb.0: // %entry
@@ -791,6 +828,16 @@ entry:
791828
ret <2 x i64> %shuffle.i
792829
}
793830

831+
define <2 x ptr> @test_vzip2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
832+
; CHECK-LABEL: test_vzip2q_p0:
833+
; CHECK: // %bb.0: // %entry
834+
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
835+
; CHECK-NEXT: ret
836+
entry:
837+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
838+
ret <2 x ptr> %shuffle.i
839+
}
840+
794841
define <2 x float> @test_vzip2_f32(<2 x float> %a, <2 x float> %b) {
795842
; CHECK-LABEL: test_vzip2_f32:
796843
; CHECK: // %bb.0: // %entry
@@ -1001,6 +1048,16 @@ entry:
10011048
ret <2 x i64> %shuffle.i
10021049
}
10031050

1051+
define <2 x ptr> @test_vtrn1q_p0(<2 x ptr> %a, <2 x ptr> %b) {
1052+
; CHECK-LABEL: test_vtrn1q_p0:
1053+
; CHECK: // %bb.0: // %entry
1054+
; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
1055+
; CHECK-NEXT: ret
1056+
entry:
1057+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 0, i32 2>
1058+
ret <2 x ptr> %shuffle.i
1059+
}
1060+
10041061
define <2 x float> @test_vtrn1_f32(<2 x float> %a, <2 x float> %b) {
10051062
; CHECK-LABEL: test_vtrn1_f32:
10061063
; CHECK: // %bb.0: // %entry
@@ -1211,6 +1268,16 @@ entry:
12111268
ret <2 x i64> %shuffle.i
12121269
}
12131270

1271+
define <2 x ptr> @test_vtrn2q_p0(<2 x ptr> %a, <2 x ptr> %b) {
1272+
; CHECK-LABEL: test_vtrn2q_p0:
1273+
; CHECK: // %bb.0: // %entry
1274+
; CHECK-NEXT: zip2 v0.2d, v0.2d, v1.2d
1275+
; CHECK-NEXT: ret
1276+
entry:
1277+
%shuffle.i = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 1, i32 3>
1278+
ret <2 x ptr> %shuffle.i
1279+
}
1280+
12141281
define <2 x float> @test_vtrn2_f32(<2 x float> %a, <2 x float> %b) {
12151282
; CHECK-LABEL: test_vtrn2_f32:
12161283
; CHECK: // %bb.0: // %entry

‎llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,16 @@ entry:
1111
ret <2 x i64> %V128
1212
}
1313

14+
define <2 x ptr> @v2p0(<2 x ptr> %a) {
15+
; CHECK-LABEL: v2p0:
16+
; CHECK: // %bb.0: // %entry
17+
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
18+
; CHECK-NEXT: ret
19+
entry:
20+
%V128 = shufflevector <2 x ptr> %a, <2 x ptr> undef, <2 x i32> <i32 1, i32 0>
21+
ret <2 x ptr> %V128
22+
}
23+
1424
define <4 x i32> @v4i32(<4 x i32> %a) {
1525
; CHECK-LABEL: v4i32:
1626
; CHECK: // %bb.0: // %entry
@@ -46,9 +56,9 @@ entry:
4656
define <8 x i16> @v8i16_2(<4 x i16> %a, <4 x i16> %b) {
4757
; CHECK-LABEL: v8i16_2:
4858
; CHECK: // %bb.0: // %entry
49-
; CHECK-NEXT: adrp x8, .LCPI4_0
59+
; CHECK-NEXT: adrp x8, .LCPI5_0
5060
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
51-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_0]
61+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]
5262
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
5363
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
5464
; CHECK-NEXT: ret
@@ -81,9 +91,9 @@ entry:
8191
define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) {
8292
; CHECK-LABEL: v16i8_2:
8393
; CHECK: // %bb.0: // %entry
84-
; CHECK-NEXT: adrp x8, .LCPI7_0
94+
; CHECK-NEXT: adrp x8, .LCPI8_0
8595
; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
86-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
96+
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
8797
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
8898
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
8999
; CHECK-NEXT: ret

‎llvm/test/CodeGen/AArch64/neon-vector-splat.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,3 +85,13 @@ define <2 x i64> @shuffle7(ptr %P) {
8585
%sv2i64 = shufflevector <2 x i64> %lv2i64, <2 x i64> undef, <2 x i32> zeroinitializer
8686
ret <2 x i64> %sv2i64
8787
}
88+
89+
define <2 x ptr> @shuffle8(ptr %P) {
90+
; CHECK-LABEL: shuffle8:
91+
; CHECK: // %bb.0:
92+
; CHECK-NEXT: ld1r { v0.2d }, [x0]
93+
; CHECK-NEXT: ret
94+
%lv2ptr = load <2 x ptr>, ptr %P
95+
%sv2ptr = shufflevector <2 x ptr> %lv2ptr, <2 x ptr> undef, <2 x i32> zeroinitializer
96+
ret <2 x ptr> %sv2ptr
97+
}

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