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SpencerAbsonSpencerAbson
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[AArch64] Add assembly/disassembly for SVE zeroing int-float conversions (#113605)
This patch adds assembly/disassembly for the following predicated SVE2.2 instructions - SCVTF (zeroing) - UCVTF (zeroing) - FCVTZS (zeroing) - FCVTZU (zeroing) - FLOGB (zeroing) - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
1 parent 90cdc03 commit 403e4a2

13 files changed

+504
-1
lines changed

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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Original file line numberDiff line numberDiff line change
@@ -4227,6 +4227,15 @@ let Predicates = [HasSVE2p2orSME2p2] in {
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// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
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def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
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// Floating-point convert to integer, zeroing predicate
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defm FCVTZS_ZPzZ : sve_fp_z2op_p_zd_d<0b0, "fcvtzs">;
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defm FCVTZU_ZPzZ : sve_fp_z2op_p_zd_d<0b1, "fcvtzu">;
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// Integer convert to floating-point, zeroing predicate
4234+
defm SCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b0, "scvtf">;
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defm UCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b1, "ucvtf">;
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// Signed integer base 2 logarithm of fp value, zeroing predicate
4237+
defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;
4238+
42304239
// Floating point round to integral fp value in integer size range
42314240
// Merging
42324241
defm FRINT32Z_ZPmZ : sve_fp_2op_p_zd_frint<0b00, "frint32z">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 26 additions & 0 deletions
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@@ -3181,6 +3181,32 @@ multiclass sve_fp_z2op_p_zd_frint<bits<2> opc, string asm> {
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def _D : sve_fp_z2op_p_zd<{ 0b0010, opc{1}, 1, opc{0} }, asm, ZPR64, ZPR64>;
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}
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3184+
multiclass sve_fp_z2op_p_zd_d<bit U, string asm> {
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def _HtoH : sve_fp_z2op_p_zd<{ 0b011101, U }, asm, ZPR16, ZPR16>;
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def _HtoS : sve_fp_z2op_p_zd<{ 0b011110, U }, asm, ZPR16, ZPR32>;
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def _HtoD : sve_fp_z2op_p_zd<{ 0b011111, U }, asm, ZPR16, ZPR64>;
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def _StoS : sve_fp_z2op_p_zd<{ 0b101110, U }, asm, ZPR32, ZPR32>;
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def _StoD : sve_fp_z2op_p_zd<{ 0b111110, U }, asm, ZPR32, ZPR64>;
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def _DtoS : sve_fp_z2op_p_zd<{ 0b111100, U }, asm, ZPR64, ZPR32>;
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def _DtoD : sve_fp_z2op_p_zd<{ 0b111111, U }, asm, ZPR64, ZPR64>;
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}
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multiclass sve_fp_z2op_p_zd_c<bit U, string asm> {
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def _HtoH : sve_fp_z2op_p_zd<{ 0b011001, U }, asm, ZPR16, ZPR16>;
3196+
def _StoH : sve_fp_z2op_p_zd<{ 0b011010, U }, asm, ZPR32, ZPR16>;
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def _StoS : sve_fp_z2op_p_zd<{ 0b101010, U }, asm, ZPR32, ZPR32>;
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def _StoD : sve_fp_z2op_p_zd<{ 0b111000, U }, asm, ZPR32, ZPR64>;
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def _DtoS : sve_fp_z2op_p_zd<{ 0b111010, U }, asm, ZPR64, ZPR32>;
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def _DtoH : sve_fp_z2op_p_zd<{ 0b011011, U }, asm, ZPR64, ZPR16>;
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def _DtoD : sve_fp_z2op_p_zd<{ 0b111011, U }, asm, ZPR64, ZPR64>;
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}
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multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
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def _H : sve_fp_z2op_p_zd<0b0011001, asm, ZPR16, ZPR16>;
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def _S : sve_fp_z2op_p_zd<0b0011010, asm, ZPR32, ZPR32>;
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def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
31853211
// SVE Integer Arithmetic - Binary Predicated Group
31863212
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE2/flogb-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ flogb z0.b, p0/m, z0.b
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// Invalid predicate operation
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flogb z0.s, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
1818
// CHECK-NEXT: flogb z0.s, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2020

‎llvm/test/MC/AArch64/SVE2p2/fcvtzs_z-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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fcvtzs z0.h, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzs z0.h, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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fcvtzs z0.h, p8/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: fcvtzs z0.h, p8/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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fcvtzs z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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fcvtzs z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/fcvtzs_z.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// convert from half
18+
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fcvtzs z0.h, p0/z, z0.h // 01100100-01011110-11000000-00000000
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// CHECK-INST: fcvtzs z0.h, p0/z, z0.h
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// CHECK-ENCODING: [0x00,0xc0,0x5e,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 645ec000 <unknown>
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fcvtzs z23.s, p3/z, z13.h // 01100100-01011111-10001101-10110111
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// CHECK-INST: fcvtzs z23.s, p3/z, z13.h
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// CHECK-ENCODING: [0xb7,0x8d,0x5f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 645f8db7 <unknown>
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fcvtzs z31.d, p7/z, z31.h // 01100100-01011111-11011111-11111111
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// CHECK-INST: fcvtzs z31.d, p7/z, z31.h
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// CHECK-ENCODING: [0xff,0xdf,0x5f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 645fdfff <unknown>
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// convert from single
38+
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fcvtzs z0.s, p0/z, z0.s // 01100100-10011111-10000000-00000000
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// CHECK-INST: fcvtzs z0.s, p0/z, z0.s
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// CHECK-ENCODING: [0x00,0x80,0x9f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 649f8000 <unknown>
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fcvtzs z21.d, p5/z, z10.s // 01100100-11011111-10010101-01010101
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// CHECK-INST: fcvtzs z21.d, p5/z, z10.s
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// CHECK-ENCODING: [0x55,0x95,0xdf,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 64df9555 <unknown>
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// convert from double
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fcvtzs z23.s, p3/z, z13.d // 01100100-11011110-10001101-10110111
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// CHECK-INST: fcvtzs z23.s, p3/z, z13.d
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// CHECK-ENCODING: [0xb7,0x8d,0xde,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 64de8db7 <unknown>
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fcvtzs z31.d, p7/z, z31.d // 01100100-11011111-11011111-11111111
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// CHECK-INST: fcvtzs z31.d, p7/z, z31.d
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// CHECK-ENCODING: [0xff,0xdf,0xdf,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 64dfdfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/fcvtzu_z-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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fcvtzu z0.h, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvtzu z0.h, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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fcvtzu z0.h, p8/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: fcvtzu z0.h, p8/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
22+
// Negative tests for instructions that are incompatible with movprfx
23+
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movprfx z0.d, p0/z, z7.d
25+
fcvtzu z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
29+
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movprfx z0, z7
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fcvtzu z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/fcvtzu_z.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// convert from half
18+
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fcvtzu z0.h, p0/z, z0.h // 01100100-01011110-11100000-00000000
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// CHECK-INST: fcvtzu z0.h, p0/z, z0.h
21+
// CHECK-ENCODING: [0x00,0xe0,0x5e,0x64]
22+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
23+
// CHECK-UNKNOWN: 645ee000 <unknown>
24+
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fcvtzu z21.s, p5/z, z10.h // 01100100-01011111-10110101-01010101
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// CHECK-INST: fcvtzu z21.s, p5/z, z10.h
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// CHECK-ENCODING: [0x55,0xb5,0x5f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
29+
// CHECK-UNKNOWN: 645fb555 <unknown>
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fcvtzu z23.d, p3/z, z13.h // 01100100-01011111-11101101-10110111
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// CHECK-INST: fcvtzu z23.d, p3/z, z13.h
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// CHECK-ENCODING: [0xb7,0xed,0x5f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 645fedb7 <unknown>
36+
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// convert from single
38+
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fcvtzu z21.s, p5/z, z10.s // 01100100-10011111-10110101-01010101
40+
// CHECK-INST: fcvtzu z21.s, p5/z, z10.s
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// CHECK-ENCODING: [0x55,0xb5,0x9f,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
43+
// CHECK-UNKNOWN: 649fb555 <unknown>
44+
45+
fcvtzu z31.d, p7/z, z31.s // 01100100-11011111-10111111-11111111
46+
// CHECK-INST: fcvtzu z31.d, p7/z, z31.s
47+
// CHECK-ENCODING: [0xff,0xbf,0xdf,0x64]
48+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 64dfbfff <unknown>
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// convert from double
52+
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fcvtzu z0.s, p0/z, z0.d // 01100100-11011110-10100000-00000000
54+
// CHECK-INST: fcvtzu z0.s, p0/z, z0.d
55+
// CHECK-ENCODING: [0x00,0xa0,0xde,0x64]
56+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
57+
// CHECK-UNKNOWN: 64dea000 <unknown>
58+
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fcvtzu z31.d, p7/z, z31.d // 01100100-11011111-11111111-11111111
60+
// CHECK-INST: fcvtzu z31.d, p7/z, z31.d
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// CHECK-ENCODING: [0xff,0xff,0xdf,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 64dfffff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/flogb_z-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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3+
// --------------------------------------------------------------------------//
4+
// Invalid element width
5+
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flogb z0.b, p0/z, z0.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: flogb z0.b, p0/z, z0.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
flogb z0.h, p0/z, z0.s
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: flogb z0.h, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
flogb z0.s, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: flogb z0.s, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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flogb z0.d, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: flogb z0.d, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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flogb z0.h, p8/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
31+
// CHECK-NEXT: flogb z0.h, p8/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
36+
37+
movprfx z0.d, p0/z, z7.d
38+
flogb z0.d, p0/z, z3.d
39+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
40+
// CHECK-NEXT: flogb z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
42+
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movprfx z0, z7
44+
flogb z0.d, p0/z, z3.d
45+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
46+
// CHECK-NEXT: flogb z0.d, p0/z, z3.d
47+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/flogb_z.s

Lines changed: 33 additions & 0 deletions
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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flogb z0.h, p0/z, z0.h // 01100100-00011110-10100000-00000000
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// CHECK-INST: flogb z0.h, p0/z, z0.h
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// CHECK-ENCODING: [0x00,0xa0,0x1e,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641ea000 <unknown>
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flogb z23.s, p3/z, z13.s // 01100100-00011110-11001101-10110111
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// CHECK-INST: flogb z23.s, p3/z, z13.s
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// CHECK-ENCODING: [0xb7,0xcd,0x1e,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641ecdb7 <unknown>
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flogb z31.d, p7/z, z31.d // 01100100-00011110-11111111-11111111
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// CHECK-INST: flogb z31.d, p7/z, z31.d
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// CHECK-ENCODING: [0xff,0xff,0x1e,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641effff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/scvtf_z-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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scvtf z0.s, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.s, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf z0.d, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: scvtf z0.d, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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scvtf z0.h, p8/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: scvtf z0.h, p8/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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scvtf z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: scvtf z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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scvtf z0.d, p0/z, z3.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: scvtf z0.d, p0/z, z3.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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