@@ -1308,55 +1308,15 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) {
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unsigned VLOpNum = RISCVII::getVLOpNum (MI.getDesc ());
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MachineOperand &VLOp = MI.getOperand (VLOpNum);
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- unsigned VLOpNum = RISCVII::getVLOpNum (MI.getDesc ());
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- MachineOperand &VLOp = MI.getOperand (VLOpNum);
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-
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- if (!RISCV::isVLKnownLE (*CommonVL, VLOp)) {
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- LLVM_DEBUG (dbgs () << " Abort due to CommonVL not <= VLOp.\n " );
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- continue ;
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- }
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-
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- if (CommonVL->isIdenticalTo (VLOp)) {
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- LLVM_DEBUG (
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- dbgs ()
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- << " Abort due to CommonVL == VLOp, no point in reducing.\n " );
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- continue ;
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- }
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-
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- if (CommonVL->isImm ()) {
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- LLVM_DEBUG (dbgs () << " Reduce VL from " << VLOp << " to "
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- << CommonVL->getImm () << " for " << MI << " \n " );
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- VLOp.ChangeToImmediate (CommonVL->getImm ());
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- } else {
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- const MachineInstr *VLMI = MRI->getVRegDef (CommonVL->getReg ());
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- if (!MDT->dominates (VLMI, &MI))
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- continue ;
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- LLVM_DEBUG (
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- dbgs () << " Reduce VL from " << VLOp << " to "
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- << printReg (CommonVL->getReg (), MRI->getTargetRegisterInfo ())
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- << " for " << MI << " \n " );
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-
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- // All our checks passed. We can reduce VL.
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- VLOp.ChangeToRegister (CommonVL->getReg (), false );
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- }
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-
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- MadeChange = true ;
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-
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- // Now add all inputs to this instruction to the worklist.
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- for (auto &Op : MI.operands ()) {
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- if (!Op.isReg () || !Op.isUse () || !Op.getReg ().isVirtual ())
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- continue ;
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-
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- if (!isVectorRegClass (Op.getReg (), MRI))
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- continue ;
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-
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- MachineInstr *DefMI = MRI->getVRegDef (Op.getReg ());
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-
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- if (!isCandidate (*DefMI))
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- continue ;
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+ if (!RISCV::isVLKnownLE (*CommonVL, VLOp)) {
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+ LLVM_DEBUG (dbgs () << " Abort due to CommonVL not <= VLOp.\n " );
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+ return false ;
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+ }
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- Worklist.insert (DefMI);
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- }
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+ if (CommonVL->isIdenticalTo (VLOp)) {
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+ LLVM_DEBUG (
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+ dbgs () << " Abort due to CommonVL == VLOp, no point in reducing.\n " );
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+ return false ;
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}
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if (CommonVL->isImm ()) {
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