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[LLVM][AARCH64] Add assembly/disassembly of zeroing convert instructions (#113292)
This patch adds the zeroing predicate forms (Pg/z) of the following instructions: - FCVTXNT - FCVTNT - FCVTLT - BFCVTNT As specified in https://developer.arm.com/documentation/ddi0602. Co-authored-by: Spencer Abson [[email protected]](mailto:[email protected])
1 parent a59f712 commit 2c5208a

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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

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@@ -4199,6 +4199,22 @@ defm TBXQ_ZZZ : sve2_int_perm_tbx<"tbxq", 0b10, int_aarch64_sve_tbxq>;
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defm TBLQ_ZZZ : sve2p1_tblq<"tblq", int_aarch64_sve_tblq>;
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} // End HasSVE2p1_or_HasSME2p1
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//===----------------------------------------------------------------------===//
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// SME2.2 or SVE2.2 instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSVE2p2orSME2p2] in {
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// SVE2p2 floating-point convert precision down (placing odd), zeroing predicate
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defm FCVTNT_ZPzZ : sve_fp_fcvtntz<"fcvtnt">;
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def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>;
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// SVE2p2 floating-point convert precision up, zeroing predicate
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defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt">;
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// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
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def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
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} // End HasSME2p2orSVE2p2
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//===----------------------------------------------------------------------===//
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// SVE2 FP8 instructions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

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@@ -2735,6 +2735,37 @@ multiclass sve2_fp_convert_down_odd_rounding_top<string asm, string op> {
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def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
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}
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class sve_fp_fcvt2z<bits<4> opc, string asm, ZPRRegOp zprty1,
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ZPRRegOp zprty2>
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: I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn),
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asm, "\t$Zd, $Pg/z, $Zn",
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"",
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[]>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zn;
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bits<3> Pg;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = opc{3-2};
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let Inst{21-18} = 0b0000;
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let Inst{17-16} = opc{1-0};
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let Inst{15-13} = 0b101;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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let hasSideEffects = 0;
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let mayRaiseFPException = 1;
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}
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multiclass sve_fp_fcvtntz<string asm> {
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def _StoH : sve_fp_fcvt2z<0b1000, asm, ZPR16, ZPR32>;
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def _DtoS : sve_fp_fcvt2z<0b1110, asm, ZPR32, ZPR64>;
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}
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multiclass sve_fp_fcvtltz<string asm> {
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def _HtoS : sve_fp_fcvt2z<0b1001, asm, ZPR32, ZPR16>;
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def _StoD : sve_fp_fcvt2z<0b1111, asm, ZPR64, ZPR32>;
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}
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//===----------------------------------------------------------------------===//
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// SVE2 Floating Point Pairwise Group
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//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE/bfcvtnt-diagnostics.s‎

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@@ -11,7 +11,7 @@ bfcvtnt z0.h, p0/m, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvtnt z0.h, p0/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SVE2/fcvtlt-diagnostics.s‎

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@@ -39,7 +39,7 @@ fcvtlt z0.q, p0/m, z0.d
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// Invalid predicate operation
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fcvtlt z0.s, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
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// CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SVE2/fcvtnt-diagnostics.s‎

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@@ -39,7 +39,7 @@ fcvtnt z0.d, p0/m, z0.q
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// Invalid predicate operation
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fcvtnt z0.h, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
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// CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s‎

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@@ -44,7 +44,7 @@ fcvtxnt z0.d, p0/m, z0.q
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// Invalid predicate operation
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fcvtxnt z0.s, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
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// CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SVE2p2/bfcvtnt_z-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid element width
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bfcvtnt z0.s, p0/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvtnt z0.s, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvtnt z0.d, p0/z, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvtnt z0.d, p0/z, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvtnt z0.h, p0/z, z1.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvtnt z0.h, p0/z, z1.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvtnt z0.h, p0/z, z1.q
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.q
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}
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// --------------------------------------------------------------------------//
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// Predicate not in restricted predicate range
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bfcvtnt z0.h, p8/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: bfcvtnt z0.h, p8/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.h, p0/m, z7.h
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bfcvtnt z0.h, p0/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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bfcvtnt z0.h, p0/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bfcvtnt z0.h, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/bfcvtnt_z.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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bfcvtnt z0.h, p0/z, z0.s // 01100100-10000010-10100000-00000000
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// CHECK-INST: bfcvtnt z0.h, p0/z, z0.s
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// CHECK-ENCODING: [0x00,0xa0,0x82,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 6482a000 <unknown>
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bfcvtnt z23.h, p3/z, z13.s // 01100100-10000010-10101101-10110111
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// CHECK-INST: bfcvtnt z23.h, p3/z, z13.s
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// CHECK-ENCODING: [0xb7,0xad,0x82,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 6482adb7 <unknown>
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bfcvtnt z31.h, p7/z, z31.s // 01100100-10000010-10111111-11111111
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// CHECK-INST: bfcvtnt z31.h, p7/z, z31.s
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// CHECK-ENCODING: [0xff,0xbf,0x82,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 6482bfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/directive-arch-negative.s‎

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// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch armv9-a+sve2p2
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.arch armv9-a+nosve2p2
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bfcvtnt z23.h, p3/z, z13.s
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// CHECK: error: instruction requires: sme2p2 or sve2p2
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// CHECK-NEXT: bfcvtnt z23.h, p3/z, z13.s

‎llvm/test/MC/AArch64/SVE2p2/directive-arch.s‎

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// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch armv9-a+sve2p2
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bfcvtnt z23.h, p3/z, z13.s
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// CHECK: bfcvtnt z23.h, p3/z, z13.s

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