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11 files changed

+48
-48
lines changed

11 files changed

+48
-48
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -834,9 +834,9 @@ class TargetTransformInfo {
834834
/// If the AM is not supported, it returns a negative value.
835835
/// TODO: Handle pre/postinc as well.
836836
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
837-
int64_t BaseOffset, bool HasBaseReg,
838-
int64_t Scale, unsigned AddrSpace = 0,
839-
int64_t ScalableOffset = 0) const;
837+
StackOffset BaseOffset, bool HasBaseReg,
838+
int64_t Scale,
839+
unsigned AddrSpace = 0) const;
840840

841841
/// Return true if the loop strength reduce pass should make
842842
/// Instruction* based TTI queries to isLegalAddressingMode(). This is
@@ -1891,10 +1891,9 @@ class TargetTransformInfo::Concept {
18911891
virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
18921892
virtual bool prefersVectorizedAddressing() = 0;
18931893
virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
1894-
int64_t BaseOffset,
1894+
StackOffset BaseOffset,
18951895
bool HasBaseReg, int64_t Scale,
1896-
unsigned AddrSpace,
1897-
int64_t ScalableOffset) = 0;
1896+
unsigned AddrSpace) = 0;
18981897
virtual bool LSRWithInstrQueries() = 0;
18991898
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
19001899
virtual bool isProfitableToHoist(Instruction *I) = 0;
@@ -2404,11 +2403,11 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
24042403
return Impl.prefersVectorizedAddressing();
24052404
}
24062405
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2407-
int64_t BaseOffset, bool HasBaseReg,
2408-
int64_t Scale, unsigned AddrSpace,
2409-
int64_t ScalableOffset) override {
2406+
StackOffset BaseOffset, bool HasBaseReg,
2407+
int64_t Scale,
2408+
unsigned AddrSpace) override {
24102409
return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2411-
AddrSpace, ScalableOffset);
2410+
AddrSpace);
24122411
}
24132412
bool LSRWithInstrQueries() override { return Impl.LSRWithInstrQueries(); }
24142413
bool isTruncateFree(Type *Ty1, Type *Ty2) override {

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ class Function;
3232
/// Base class for use as a mix-in that aids implementing
3333
/// a TargetTransformInfo-compatible class.
3434
class TargetTransformInfoImplBase {
35+
friend class TargetTransformInfo;
36+
3537
protected:
3638
typedef TargetTransformInfo TTI;
3739

@@ -326,12 +328,13 @@ class TargetTransformInfoImplBase {
326328
bool prefersVectorizedAddressing() const { return true; }
327329

328330
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
329-
int64_t BaseOffset, bool HasBaseReg,
330-
int64_t Scale, unsigned AddrSpace,
331-
int64_t ScalableOffset) const {
331+
StackOffset BaseOffset, bool HasBaseReg,
332+
int64_t Scale,
333+
unsigned AddrSpace) const {
332334
// Guess that all legal addressing mode are free.
333-
if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
334-
AddrSpace, /*I=*/nullptr, ScalableOffset))
335+
if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg,
336+
Scale, AddrSpace, /*I=*/nullptr,
337+
BaseOffset.getScalable()))
335338
return 0;
336339
return -1;
337340
}

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -403,15 +403,14 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
403403
}
404404

405405
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
406-
int64_t BaseOffset, bool HasBaseReg,
407-
int64_t Scale, unsigned AddrSpace,
408-
int64_t ScalableOffset) {
406+
StackOffset BaseOffset, bool HasBaseReg,
407+
int64_t Scale, unsigned AddrSpace) {
409408
TargetLoweringBase::AddrMode AM;
410409
AM.BaseGV = BaseGV;
411-
AM.BaseOffs = BaseOffset;
410+
AM.BaseOffs = BaseOffset.getFixed();
412411
AM.HasBaseReg = HasBaseReg;
413412
AM.Scale = Scale;
414-
AM.ScalableOffset = ScalableOffset;
413+
AM.ScalableOffset = BaseOffset.getScalable();
415414
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
416415
return 0;
417416
return -1;

‎llvm/lib/Analysis/TargetTransformInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -531,10 +531,10 @@ bool TargetTransformInfo::prefersVectorizedAddressing() const {
531531
}
532532

533533
InstructionCost TargetTransformInfo::getScalingFactorCost(
534-
Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
535-
int64_t Scale, unsigned AddrSpace, int64_t ScalableOffset) const {
534+
Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
535+
int64_t Scale, unsigned AddrSpace) const {
536536
InstructionCost Cost = TTIImpl->getScalingFactorCost(
537-
Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace, ScalableOffset);
537+
Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
538538
assert(Cost >= 0 && "TTI should not produce negative costs!");
539539
return Cost;
540540
}

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4160,9 +4160,10 @@ bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) {
41604160
return NumInsns >= SVETailFoldInsnThreshold;
41614161
}
41624162

4163-
InstructionCost AArch64TTIImpl::getScalingFactorCost(
4164-
Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
4165-
int64_t Scale, unsigned AddrSpace, int64_t ScalableOffset) const {
4163+
InstructionCost
4164+
AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
4165+
StackOffset BaseOffset, bool HasBaseReg,
4166+
int64_t Scale, unsigned AddrSpace) const {
41664167
// Scaling factors are not free at all.
41674168
// Operands | Rt Latency
41684169
// -------------------------------------------
@@ -4172,10 +4173,10 @@ InstructionCost AArch64TTIImpl::getScalingFactorCost(
41724173
// Rt, [Xn, Wm, <extend> #imm] |
41734174
TargetLoweringBase::AddrMode AM;
41744175
AM.BaseGV = BaseGV;
4175-
AM.BaseOffs = BaseOffset;
4176+
AM.BaseOffs = BaseOffset.getFixed();
41764177
AM.HasBaseReg = HasBaseReg;
41774178
AM.Scale = Scale;
4178-
AM.ScalableOffset = ScalableOffset;
4179+
AM.ScalableOffset = BaseOffset.getScalable();
41794180
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
41804181
// Scale represents reg2 * scale, thus account for 1 if
41814182
// it is not equal to 0 or 1.

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -407,9 +407,8 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
407407
/// If the AM is supported, the return value must be >= 0.
408408
/// If the AM is not supported, it returns a negative value.
409409
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
410-
int64_t BaseOffset, bool HasBaseReg,
411-
int64_t Scale, unsigned AddrSpace,
412-
int64_t ScalableOffset) const;
410+
StackOffset BaseOffset, bool HasBaseReg,
411+
int64_t Scale, unsigned AddrSpace) const;
413412
/// @}
414413

415414
bool enableSelectOptimize() { return ST->enableSelectOptimize(); }

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2571,16 +2571,15 @@ bool ARMTTIImpl::preferPredicatedReductionSelect(
25712571
}
25722572

25732573
InstructionCost ARMTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2574-
int64_t BaseOffset,
2574+
StackOffset BaseOffset,
25752575
bool HasBaseReg, int64_t Scale,
2576-
unsigned AddrSpace,
2577-
int64_t ScalableOffset) const {
2576+
unsigned AddrSpace) const {
25782577
TargetLoweringBase::AddrMode AM;
25792578
AM.BaseGV = BaseGV;
2580-
AM.BaseOffs = BaseOffset;
2579+
AM.BaseOffs = BaseOffset.getFixed();
25812580
AM.HasBaseReg = HasBaseReg;
25822581
AM.Scale = Scale;
2583-
AM.ScalableOffset = ScalableOffset;
2582+
assert(!BaseOffset.getScalable() && "Scalable offsets unsupported");
25842583
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) {
25852584
if (ST->hasFPAO())
25862585
return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster

‎llvm/lib/Target/ARM/ARMTargetTransformInfo.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -303,9 +303,8 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
303303
/// If the AM is supported, the return value must be >= 0.
304304
/// If the AM is not supported, the return value must be negative.
305305
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
306-
int64_t BaseOffset, bool HasBaseReg,
307-
int64_t Scale, unsigned AddrSpace,
308-
int64_t ScalableOffset) const;
306+
StackOffset BaseOffset, bool HasBaseReg,
307+
int64_t Scale, unsigned AddrSpace) const;
309308

310309
bool maybeLoweredToCall(Instruction &I);
311310
bool isLoweredToCall(const Function *F);

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6708,10 +6708,9 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost(
67086708
}
67096709

67106710
InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
6711-
int64_t BaseOffset,
6711+
StackOffset BaseOffset,
67126712
bool HasBaseReg, int64_t Scale,
6713-
unsigned AddrSpace,
6714-
int64_t ScalableOffset) const {
6713+
unsigned AddrSpace) const {
67156714
// Scaling factors are not free at all.
67166715
// An indexed folded instruction, i.e., inst (reg1, reg2, scale),
67176716
// will take 2 allocations in the out of order engine instead of 1
@@ -6732,9 +6731,10 @@ InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
67326731
// vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
67336732
TargetLoweringBase::AddrMode AM;
67346733
AM.BaseGV = BaseGV;
6735-
AM.BaseOffs = BaseOffset;
6734+
AM.BaseOffs = BaseOffset.getFixed();
67366735
AM.HasBaseReg = HasBaseReg;
67376736
AM.Scale = Scale;
6737+
assert(!BaseOffset.getScalable() && "Scalable offsets unsupported");
67386738
if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace))
67396739
// Scale represents reg2 * scale, thus account for 1
67406740
// as soon as we use a second register.

‎llvm/lib/Target/X86/X86TargetTransformInfo.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -253,9 +253,8 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
253253
/// If the AM is supported, the return value must be >= 0.
254254
/// If the AM is not supported, it returns a negative value.
255255
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
256-
int64_t BaseOffset, bool HasBaseReg,
257-
int64_t Scale, unsigned AddrSpace,
258-
int64_t ScalableOffset) const;
256+
StackOffset BaseOffset, bool HasBaseReg,
257+
int64_t Scale, unsigned AddrSpace) const;
259258

260259
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
261260
const TargetTransformInfo::LSRCost &C2);

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