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[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)
They have been superseded by llvm.amdgcn.raw.buffer.* and llvm.amdgcn.struct.buffer.*.
1 parent d319fc4 commit 18ec885

39 files changed

+155
-4445
lines changed

‎llvm/docs/TableGen/BackGuide.rst

+1-1
Original file line numberDiff line numberDiff line change
@@ -761,7 +761,7 @@ over time. The output looks like this.
761761
762762
-------------------- Global Variables (5) --------------------
763763
764-
AMDGPUBufferIntrinsics = [int_amdgcn_buffer_load_format, ...
764+
AMDGPUBufferIntrinsics = [int_amdgcn_s_buffer_load, ...
765765
AMDGPUImageDimAtomicIntrinsics = [int_amdgcn_image_atomic_swap_1d, ...
766766
...
767767
-------------------- Classes (758) --------------------

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

+3-107
Original file line numberDiff line numberDiff line change
@@ -1083,18 +1083,6 @@ def int_amdgcn_make_buffer_rsrc : DefaultAttrsIntrinsic <
10831083

10841084
defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = {
10851085

1086-
class AMDGPUBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrinsic <
1087-
[data_ty],
1088-
[llvm_v4i32_ty, // rsrc(SGPR)
1089-
llvm_i32_ty, // vindex(VGPR)
1090-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1091-
llvm_i1_ty, // glc(imm)
1092-
llvm_i1_ty], // slc(imm)
1093-
[IntrReadMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "", [SDNPMemOperand]>,
1094-
AMDGPURsrcIntrinsic<0>;
1095-
def int_amdgcn_buffer_load_format : AMDGPUBufferLoad<llvm_anyfloat_ty>;
1096-
def int_amdgcn_buffer_load : AMDGPUBufferLoad;
1097-
10981086
// Generate a buffer_load instruction that may be optimized to s_buffer_load if
10991087
// the offset argument is uniform.
11001088
def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
@@ -1111,25 +1099,12 @@ def int_amdgcn_s_buffer_load : DefaultAttrsIntrinsic <
11111099
[IntrNoMem, ImmArg<ArgIndex<2>>]>,
11121100
AMDGPURsrcIntrinsic<0>;
11131101

1114-
class AMDGPUBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntrinsic <
1115-
[],
1116-
[data_ty, // vdata(VGPR)
1117-
llvm_v4i32_ty, // rsrc(SGPR)
1118-
llvm_i32_ty, // vindex(VGPR)
1119-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1120-
llvm_i1_ty, // glc(imm)
1121-
llvm_i1_ty], // slc(imm)
1122-
[IntrWriteMem, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], "", [SDNPMemOperand]>,
1123-
AMDGPURsrcIntrinsic<1>;
1124-
def int_amdgcn_buffer_store_format : AMDGPUBufferStore<llvm_anyfloat_ty>;
1125-
def int_amdgcn_buffer_store : AMDGPUBufferStore;
1126-
1127-
// New buffer intrinsics with separate raw and struct variants. The raw
1102+
// Buffer intrinsics with separate raw and struct variants. The raw
11281103
// variant never has an index. The struct variant always has an index, even if
11291104
// it is const 0. A struct intrinsic with constant 0 index is different to the
11301105
// corresponding raw intrinsic on gfx9+ because the behavior of bound checking
11311106
// and swizzling changes depending on whether idxen is set in the instruction.
1132-
// These new instrinsics also keep the offset and soffset arguments separate as
1107+
// These instrinsics also keep the offset and soffset arguments separate as
11331108
// they behave differently in bounds checking and swizzling.
11341109

11351110
// The versions of these intrinsics that take <4 x i32> arguments are deprecated
@@ -1489,41 +1464,7 @@ def int_amdgcn_struct_buffer_atomic_fmax : AMDGPUStructBufferAtomic<llvm_anyfloa
14891464
def int_amdgcn_struct_ptr_buffer_atomic_fmin : AMDGPUStructPtrBufferAtomic<llvm_anyfloat_ty>;
14901465
def int_amdgcn_struct_ptr_buffer_atomic_fmax : AMDGPUStructPtrBufferAtomic<llvm_anyfloat_ty>;
14911466

1492-
// Obsolescent tbuffer intrinsics.
1493-
def int_amdgcn_tbuffer_load : DefaultAttrsIntrinsic <
1494-
[llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1495-
[llvm_v4i32_ty, // rsrc(SGPR)
1496-
llvm_i32_ty, // vindex(VGPR)
1497-
llvm_i32_ty, // voffset(VGPR)
1498-
llvm_i32_ty, // soffset(SGPR)
1499-
llvm_i32_ty, // offset(imm)
1500-
llvm_i32_ty, // dfmt(imm)
1501-
llvm_i32_ty, // nfmt(imm)
1502-
llvm_i1_ty, // glc(imm)
1503-
llvm_i1_ty], // slc(imm)
1504-
[IntrReadMem,
1505-
ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>,
1506-
ImmArg<ArgIndex<7>>, ImmArg<ArgIndex<8>>], "", [SDNPMemOperand]>,
1507-
AMDGPURsrcIntrinsic<0>;
1508-
1509-
def int_amdgcn_tbuffer_store : DefaultAttrsIntrinsic <
1510-
[],
1511-
[llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1512-
llvm_v4i32_ty, // rsrc(SGPR)
1513-
llvm_i32_ty, // vindex(VGPR)
1514-
llvm_i32_ty, // voffset(VGPR)
1515-
llvm_i32_ty, // soffset(SGPR)
1516-
llvm_i32_ty, // offset(imm)
1517-
llvm_i32_ty, // dfmt(imm)
1518-
llvm_i32_ty, // nfmt(imm)
1519-
llvm_i1_ty, // glc(imm)
1520-
llvm_i1_ty], // slc(imm)
1521-
[IntrWriteMem, ImmArg<ArgIndex<5>>,
1522-
ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>,
1523-
ImmArg<ArgIndex<8>>, ImmArg<ArgIndex<9>>], "", [SDNPMemOperand]>,
1524-
AMDGPURsrcIntrinsic<1>;
1525-
1526-
// New tbuffer intrinsics, with:
1467+
// tbuffer intrinsics, with:
15271468
// - raw and struct variants
15281469
// - joint format field
15291470
// - joint cachepolicy field
@@ -1670,51 +1611,6 @@ def int_amdgcn_struct_tbuffer_store : DefaultAttrsIntrinsic <
16701611
ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>], "", [SDNPMemOperand]>,
16711612
AMDGPURsrcIntrinsic<1>;
16721613

1673-
class AMDGPUBufferAtomic : Intrinsic <
1674-
[llvm_anyint_ty],
1675-
[LLVMMatchType<0>, // vdata(VGPR)
1676-
llvm_v4i32_ty, // rsrc(SGPR)
1677-
llvm_i32_ty, // vindex(VGPR)
1678-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1679-
llvm_i1_ty], // slc(imm)
1680-
[ImmArg<ArgIndex<4>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1681-
AMDGPURsrcIntrinsic<1, 0>;
1682-
def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic;
1683-
def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic;
1684-
def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic;
1685-
def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic;
1686-
def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic;
1687-
def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic;
1688-
def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic;
1689-
def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic;
1690-
def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic;
1691-
def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic;
1692-
def int_amdgcn_buffer_atomic_cmpswap : Intrinsic<
1693-
[llvm_i32_ty],
1694-
[llvm_i32_ty, // src(VGPR)
1695-
llvm_i32_ty, // cmp(VGPR)
1696-
llvm_v4i32_ty, // rsrc(SGPR)
1697-
llvm_i32_ty, // vindex(VGPR)
1698-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1699-
llvm_i1_ty], // slc(imm)
1700-
[ImmArg<ArgIndex<5>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1701-
AMDGPURsrcIntrinsic<2, 0>;
1702-
1703-
def int_amdgcn_buffer_atomic_csub : AMDGPUBufferAtomic;
1704-
1705-
class AMDGPUBufferAtomicFP : Intrinsic <
1706-
[llvm_anyfloat_ty],
1707-
[LLVMMatchType<0>, // vdata(VGPR)
1708-
llvm_v4i32_ty, // rsrc(SGPR)
1709-
llvm_i32_ty, // vindex(VGPR)
1710-
llvm_i32_ty, // offset(SGPR/VGPR/imm)
1711-
llvm_i1_ty], // slc(imm)
1712-
[ImmArg<ArgIndex<4>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
1713-
AMDGPURsrcIntrinsic<1, 0>;
1714-
1715-
// Legacy form of the intrinsic. raw and struct forms should be preferred.
1716-
def int_amdgcn_buffer_atomic_fadd : AMDGPUBufferAtomicFP;
1717-
17181614
class AMDGPURawBufferLoadLDS : Intrinsic <
17191615
[],
17201616
[llvm_v4i32_ty, // rsrc(SGPR)

‎llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp

-9
Original file line numberDiff line numberDiff line change
@@ -249,63 +249,54 @@ void AMDGPUAtomicOptimizerImpl::visitIntrinsicInst(IntrinsicInst &I) {
249249
switch (I.getIntrinsicID()) {
250250
default:
251251
return;
252-
case Intrinsic::amdgcn_buffer_atomic_add:
253252
case Intrinsic::amdgcn_struct_buffer_atomic_add:
254253
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_add:
255254
case Intrinsic::amdgcn_raw_buffer_atomic_add:
256255
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_add:
257256
Op = AtomicRMWInst::Add;
258257
break;
259-
case Intrinsic::amdgcn_buffer_atomic_sub:
260258
case Intrinsic::amdgcn_struct_buffer_atomic_sub:
261259
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub:
262260
case Intrinsic::amdgcn_raw_buffer_atomic_sub:
263261
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub:
264262
Op = AtomicRMWInst::Sub;
265263
break;
266-
case Intrinsic::amdgcn_buffer_atomic_and:
267264
case Intrinsic::amdgcn_struct_buffer_atomic_and:
268265
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_and:
269266
case Intrinsic::amdgcn_raw_buffer_atomic_and:
270267
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_and:
271268
Op = AtomicRMWInst::And;
272269
break;
273-
case Intrinsic::amdgcn_buffer_atomic_or:
274270
case Intrinsic::amdgcn_struct_buffer_atomic_or:
275271
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_or:
276272
case Intrinsic::amdgcn_raw_buffer_atomic_or:
277273
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_or:
278274
Op = AtomicRMWInst::Or;
279275
break;
280-
case Intrinsic::amdgcn_buffer_atomic_xor:
281276
case Intrinsic::amdgcn_struct_buffer_atomic_xor:
282277
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_xor:
283278
case Intrinsic::amdgcn_raw_buffer_atomic_xor:
284279
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_xor:
285280
Op = AtomicRMWInst::Xor;
286281
break;
287-
case Intrinsic::amdgcn_buffer_atomic_smin:
288282
case Intrinsic::amdgcn_struct_buffer_atomic_smin:
289283
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smin:
290284
case Intrinsic::amdgcn_raw_buffer_atomic_smin:
291285
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smin:
292286
Op = AtomicRMWInst::Min;
293287
break;
294-
case Intrinsic::amdgcn_buffer_atomic_umin:
295288
case Intrinsic::amdgcn_struct_buffer_atomic_umin:
296289
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umin:
297290
case Intrinsic::amdgcn_raw_buffer_atomic_umin:
298291
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umin:
299292
Op = AtomicRMWInst::UMin;
300293
break;
301-
case Intrinsic::amdgcn_buffer_atomic_smax:
302294
case Intrinsic::amdgcn_struct_buffer_atomic_smax:
303295
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smax:
304296
case Intrinsic::amdgcn_raw_buffer_atomic_smax:
305297
case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smax:
306298
Op = AtomicRMWInst::Max;
307299
break;
308-
case Intrinsic::amdgcn_buffer_atomic_umax:
309300
case Intrinsic::amdgcn_struct_buffer_atomic_umax:
310301
case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umax:
311302
case Intrinsic::amdgcn_raw_buffer_atomic_umax:

‎llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

-5
Original file line numberDiff line numberDiff line change
@@ -1158,12 +1158,10 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
11581158
return IC.replaceInstUsesWith(II, ConstantInt::getFalse(II.getType()));
11591159
break;
11601160
}
1161-
case Intrinsic::amdgcn_buffer_store_format:
11621161
case Intrinsic::amdgcn_raw_buffer_store_format:
11631162
case Intrinsic::amdgcn_struct_buffer_store_format:
11641163
case Intrinsic::amdgcn_raw_tbuffer_store:
11651164
case Intrinsic::amdgcn_struct_tbuffer_store:
1166-
case Intrinsic::amdgcn_tbuffer_store:
11671165
case Intrinsic::amdgcn_image_store_1d:
11681166
case Intrinsic::amdgcn_image_store_1darray:
11691167
case Intrinsic::amdgcn_image_store_2d:
@@ -1376,8 +1374,6 @@ std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
13761374
std::function<void(Instruction *, unsigned, APInt, APInt &)>
13771375
SimplifyAndSetOp) const {
13781376
switch (II.getIntrinsicID()) {
1379-
case Intrinsic::amdgcn_buffer_load:
1380-
case Intrinsic::amdgcn_buffer_load_format:
13811377
case Intrinsic::amdgcn_raw_buffer_load:
13821378
case Intrinsic::amdgcn_raw_ptr_buffer_load:
13831379
case Intrinsic::amdgcn_raw_buffer_load_format:
@@ -1391,7 +1387,6 @@ std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
13911387
case Intrinsic::amdgcn_struct_ptr_buffer_load_format:
13921388
case Intrinsic::amdgcn_struct_tbuffer_load:
13931389
case Intrinsic::amdgcn_struct_ptr_tbuffer_load:
1394-
case Intrinsic::amdgcn_tbuffer_load:
13951390
return simplifyAMDGCNMemoryIntrinsicDemanded(IC, II, DemandedElts);
13961391
default: {
13971392
if (getAMDGPUImageDMaskIntrinsic(II.getIntrinsicID())) {

‎llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td

-12
Original file line numberDiff line numberDiff line change
@@ -256,17 +256,6 @@ def : SourceOfDivergence<int_amdgcn_ds_fadd>;
256256
def : SourceOfDivergence<int_amdgcn_ds_fmin>;
257257
def : SourceOfDivergence<int_amdgcn_ds_fmax>;
258258
def : SourceOfDivergence<int_amdgcn_ds_fadd_v2bf16>;
259-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_swap>;
260-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_add>;
261-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_sub>;
262-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>;
263-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>;
264-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>;
265-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>;
266-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>;
267-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>;
268-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
269-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
270259
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_swap>;
271260
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_add>;
272261
def : SourceOfDivergence<int_amdgcn_raw_buffer_atomic_sub>;
@@ -339,7 +328,6 @@ def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_fmin>;
339328
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_fmax>;
340329
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_cmpswap>;
341330
def : SourceOfDivergence<int_amdgcn_struct_ptr_buffer_atomic_cond_sub_u32>;
342-
def : SourceOfDivergence<int_amdgcn_buffer_atomic_csub>;
343331
def : SourceOfDivergence<int_amdgcn_ps_live>;
344332
def : SourceOfDivergence<int_amdgcn_live_mask>;
345333
def : SourceOfDivergence<int_amdgcn_ds_swizzle>;

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