resolve comments

Author: XinWang10

llvm/lib/Target/X86/X86InstrArithmetic.td

@@ -1322,12 +1322,12 @@ multiclass AndN<X86TypeInfo t, SDPatternOperator node, string suffix = ""> {
   def rr#suffix : ITy<0xF2, MRMSrcReg, t, (outs t.RegClass:$dst),
                       (ins t.RegClass:$src1, t.RegClass:$src2), "andn",
                       binop_ndd_args, andn_rr_p>, VVVV, Sched<[WriteALU]>,
-                     T8;
+                  T8, NoCD8;
   def rm#suffix : ITy<0xF2, MRMSrcMem, t, (outs t.RegClass:$dst),
                        (ins t.RegClass:$src1, t.MemOperand:$src2), "andn",
                        binop_ndd_args, andn_rm_p>, VVVV,
                        Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>,
-                       T8;
+                  T8, NoCD8;
 }
 
 // Complexity is reduced to give and with immediate a chance to match first.

llvm/test/MC/Disassembler/X86/apx/andn.txt

@@ -19,19 +19,19 @@
 
 # ATT:   {nf}	andnl	123(%rax,%rbx,4), %ecx, %edx
 # INTEL: {nf}	andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
-0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00
+0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b
 
 # ATT:   andnl	123(%rax,%rbx,4), %ecx, %edx
 # INTEL: andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
-0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00
+0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b
 
 # ATT:   {nf}	andnq	123(%rax,%rbx,4), %r9, %r15
 # INTEL: {nf}	andn	r15, r9, qword ptr [rax + 4*rbx + 123]
-0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00
+0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b
 
 # ATT:   andnq	123(%rax,%rbx,4), %r9, %r15
 # INTEL: andn	r15, r9, qword ptr [rax + 4*rbx + 123]
-0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00
+0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b
 
 # ATT:   andnl	%r18d, %r22d, %r26d
 # INTEL: andn	r26d, r22d, r18d

llvm/test/MC/X86/apx/andn-att.s

@@ -20,19 +20,19 @@
          {evex}	andnq	%r9, %r15, %r11
 
 # CHECK: {nf}	andnl	123(%rax,%rbx,4), %ecx, %edx
-# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b]
          {nf}	andnl	123(%rax,%rbx,4), %ecx, %edx
 
 # CHECK: {evex}	andnl	123(%rax,%rbx,4), %ecx, %edx
-# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b]
          {evex}	andnl	123(%rax,%rbx,4), %ecx, %edx
 
 # CHECK: {nf}	andnq	123(%rax,%rbx,4), %r9, %r15
-# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b]
          {nf}	andnq	123(%rax,%rbx,4), %r9, %r15
 
 # CHECK: {evex}	andnq	123(%rax,%rbx,4), %r9, %r15
-# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b]
          {evex}	andnq	123(%rax,%rbx,4), %r9, %r15
 
 # CHECK: andnl	%r18d, %r22d, %r26d

llvm/test/MC/X86/apx/andn-intel.s

@@ -17,19 +17,19 @@
          {evex}	andn	r11, r15, r9
 
 # CHECK: {nf}	andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x54,0x98,0x7b]
          {nf}	andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
 
 # CHECK: {evex}	andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x54,0x98,0x7b]
          {evex}	andn	edx, ecx, dword ptr [rax + 4*rbx + 123]
 
 # CHECK: {nf}	andn	r15, r9, qword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0x7c,0x98,0x7b]
          {nf}	andn	r15, r9, qword ptr [rax + 4*rbx + 123]
 
 # CHECK: {evex}	andn	r15, r9, qword ptr [rax + 4*rbx + 123]
-# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0x7c,0x98,0x7b]
          {evex}	andn	r15, r9, qword ptr [rax + 4*rbx + 123]
 
 # CHECK: andn	r26d, r22d, r18d