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arsenmarsenm
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clang: Update tests after InstSimplify change
Update tests after 1536e29
1 parent 456468a commit 14c44df

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2 files changed

+178
-179
lines changed

2 files changed

+178
-179
lines changed

‎clang/test/CodeGen/arm_acle.c‎

Lines changed: 49 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ void test_dbg(void) {
145145
// AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[P:%.*]])
146146
// AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[X:%.*]], ptr elementtype(i32) [[P]])
147147
// AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0
148-
// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP7:![0-9]+]]
148+
// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP3:![0-9]+]]
149149
// AArch32: __swp.exit:
150150
// AArch32-NEXT: ret void
151151
//
@@ -154,11 +154,11 @@ void test_dbg(void) {
154154
// AArch64-NEXT: br label [[DO_BODY_I:%.*]]
155155
// AArch64: do.body.i:
156156
// AArch64-NEXT: [[LDXR_I:%.*]] = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) [[P:%.*]])
157-
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[LDXR_I]] to i32
158-
// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[X:%.*]] to i64
159-
// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP2]], ptr elementtype(i32) [[P]])
157+
// AArch64-NEXT: [[TMP0:%.*]] = trunc i64 [[LDXR_I]] to i32
158+
// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64
159+
// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP1]], ptr elementtype(i32) [[P]])
160160
// AArch64-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STXR_I]], 0
161-
// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP6:![0-9]+]]
161+
// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]]
162162
// AArch64: __swp.exit:
163163
// AArch64-NEXT: ret void
164164
//
@@ -484,17 +484,17 @@ uint32_t test_rev16(uint32_t t) {
484484
// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])
485485
// AArch64-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32
486486
// AArch64-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0
487-
// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]
488-
// AArch64: if.then.i.i12.i:
487+
// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]
488+
// AArch64: if.then.i.i17.i:
489489
// AArch64-NEXT: br label [[__REV16_EXIT18_I:%.*]]
490-
// AArch64: if.end.i.i17.i:
490+
// AArch64: if.end.i.i12.i:
491491
// AArch64-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]
492492
// AArch64-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]
493493
// AArch64-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]
494494
// AArch64-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]
495495
// AArch64-NEXT: br label [[__REV16_EXIT18_I]]
496496
// AArch64: __rev16.exit18.i:
497-
// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]
497+
// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]
498498
// AArch64-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64
499499
// AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32
500500
// AArch64-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32
@@ -527,17 +527,17 @@ long test_rev16l(long t) {
527527
// ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]])
528528
// ARM-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32
529529
// ARM-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0
530-
// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]
531-
// ARM: if.then.i.i12.i:
530+
// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]]
531+
// ARM: if.then.i.i17.i:
532532
// ARM-NEXT: br label [[__REV16_EXIT18_I:%.*]]
533-
// ARM: if.end.i.i17.i:
533+
// ARM: if.end.i.i12.i:
534534
// ARM-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]]
535535
// ARM-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]
536536
// ARM-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]]
537537
// ARM-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]
538538
// ARM-NEXT: br label [[__REV16_EXIT18_I]]
539539
// ARM: __rev16.exit18.i:
540-
// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]
540+
// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ]
541541
// ARM-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64
542542
// ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32
543543
// ARM-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32
@@ -662,7 +662,7 @@ int32_t test_qsub(int32_t a, int32_t b) {
662662
extern int32_t f();
663663
// AArch32-LABEL: @test_qdbl(
664664
// AArch32-NEXT: entry:
665-
// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR7:[0-9]+]]
665+
// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR9:[0-9]+]]
666666
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[CALL]], i32 [[CALL]])
667667
// AArch32-NEXT: ret i32 [[TMP0]]
668668
//
@@ -1456,12 +1456,12 @@ uint32_t test_crc32cd(uint32_t a, uint64_t b) {
14561456
/* 10.1 Special register intrinsics */
14571457
// AArch32-LABEL: @test_rsr(
14581458
// AArch32-NEXT: entry:
1459-
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9:![0-9]+]])
1459+
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5:![0-9]+]])
14601460
// AArch32-NEXT: ret i32 [[TMP0]]
14611461
//
14621462
// AArch64-LABEL: @test_rsr(
14631463
// AArch64-NEXT: entry:
1464-
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8:![0-9]+]])
1464+
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4:![0-9]+]])
14651465
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
14661466
// AArch64-NEXT: ret i32 [[TMP1]]
14671467
//
@@ -1475,12 +1475,12 @@ uint32_t test_rsr() {
14751475

14761476
// AArch32-LABEL: @test_rsr64(
14771477
// AArch32-NEXT: entry:
1478-
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10:![0-9]+]])
1478+
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6:![0-9]+]])
14791479
// AArch32-NEXT: ret i64 [[TMP0]]
14801480
//
14811481
// AArch64-LABEL: @test_rsr64(
14821482
// AArch64-NEXT: entry:
1483-
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
1483+
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
14841484
// AArch64-NEXT: ret i64 [[TMP0]]
14851485
//
14861486
uint64_t test_rsr64() {
@@ -1494,7 +1494,7 @@ uint64_t test_rsr64() {
14941494
#ifdef __ARM_FEATURE_SYSREG128
14951495
// AArch6494D128-LABEL: @test_rsr128(
14961496
// AArch6494D128-NEXT: entry:
1497-
// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META8]])
1497+
// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META4]])
14981498
// AArch6494D128-NEXT: ret i128 [[TMP0]]
14991499
//
15001500
__uint128_t test_rsr128() {
@@ -1504,13 +1504,13 @@ __uint128_t test_rsr128() {
15041504

15051505
// AArch32-LABEL: @test_rsrp(
15061506
// AArch32-NEXT: entry:
1507-
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META11:![0-9]+]])
1507+
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META7:![0-9]+]])
15081508
// AArch32-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr
15091509
// AArch32-NEXT: ret ptr [[TMP1]]
15101510
//
15111511
// AArch64-LABEL: @test_rsrp(
15121512
// AArch64-NEXT: entry:
1513-
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META9:![0-9]+]])
1513+
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META5:![0-9]+]])
15141514
// AArch64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr
15151515
// AArch64-NEXT: ret ptr [[TMP1]]
15161516
//
@@ -1520,13 +1520,13 @@ void *test_rsrp() {
15201520

15211521
// AArch32-LABEL: @test_wsr(
15221522
// AArch32-NEXT: entry:
1523-
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[V:%.*]])
1523+
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[V:%.*]])
15241524
// AArch32-NEXT: ret void
15251525
//
15261526
// AArch64-LABEL: @test_wsr(
15271527
// AArch64-NEXT: entry:
15281528
// AArch64-NEXT: [[TMP0:%.*]] = zext i32 [[V:%.*]] to i64
1529-
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP0]])
1529+
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])
15301530
// AArch64-NEXT: ret void
15311531
//
15321532
void test_wsr(uint32_t v) {
@@ -1539,12 +1539,12 @@ void test_wsr(uint32_t v) {
15391539

15401540
// AArch32-LABEL: @test_wsr64(
15411541
// AArch32-NEXT: entry:
1542-
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[V:%.*]])
1542+
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[V:%.*]])
15431543
// AArch32-NEXT: ret void
15441544
//
15451545
// AArch64-LABEL: @test_wsr64(
15461546
// AArch64-NEXT: entry:
1547-
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[V:%.*]])
1547+
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[V:%.*]])
15481548
// AArch64-NEXT: ret void
15491549
//
15501550
void test_wsr64(uint64_t v) {
@@ -1558,7 +1558,7 @@ void test_wsr64(uint64_t v) {
15581558
#ifdef __ARM_FEATURE_SYSREG128
15591559
// AArch6494D128-LABEL: @test_wsr128(
15601560
// AArch6494D128-NEXT: entry:
1561-
// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META8]], i128 [[V:%.*]])
1561+
// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META4]], i128 [[V:%.*]])
15621562
// AArch6494D128-NEXT: ret void
15631563
//
15641564
void test_wsr128(__uint128_t v) {
@@ -1570,13 +1570,13 @@ void test_wsr128(__uint128_t v) {
15701570
// AArch32-LABEL: @test_wsrp(
15711571
// AArch32-NEXT: entry:
15721572
// AArch32-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i32
1573-
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META11]], i32 [[TMP0]])
1573+
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META7]], i32 [[TMP0]])
15741574
// AArch32-NEXT: ret void
15751575
//
15761576
// AArch64-LABEL: @test_wsrp(
15771577
// AArch64-NEXT: entry:
15781578
// AArch64-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i64
1579-
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META9]], i64 [[TMP0]])
1579+
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META5]], i64 [[TMP0]])
15801580
// AArch64-NEXT: ret void
15811581
//
15821582
void test_wsrp(void *v) {
@@ -1586,19 +1586,19 @@ void test_wsrp(void *v) {
15861586
// AArch32-LABEL: @test_rsrf(
15871587
// AArch32-NEXT: entry:
15881588
// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
1589-
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9]])
1589+
// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5]])
15901590
// AArch32-NEXT: store i32 [[TMP0]], ptr [[REF_TMP]], align 4
1591-
// AArch32-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4
1592-
// AArch32-NEXT: ret float [[TMP2]]
1591+
// AArch32-NEXT: [[TMP1:%.*]] = load float, ptr [[REF_TMP]], align 4
1592+
// AArch32-NEXT: ret float [[TMP1]]
15931593
//
15941594
// AArch64-LABEL: @test_rsrf(
15951595
// AArch64-NEXT: entry:
15961596
// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4
1597-
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
1597+
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
15981598
// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
15991599
// AArch64-NEXT: store i32 [[TMP1]], ptr [[REF_TMP]], align 4
1600-
// AArch64-NEXT: [[TMP3:%.*]] = load float, ptr [[REF_TMP]], align 4
1601-
// AArch64-NEXT: ret float [[TMP3]]
1600+
// AArch64-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4
1601+
// AArch64-NEXT: ret float [[TMP2]]
16021602
//
16031603
float test_rsrf() {
16041604
#ifdef __ARM_32BIT_STATE
@@ -1611,18 +1611,18 @@ float test_rsrf() {
16111611
// AArch32-LABEL: @test_rsrf64(
16121612
// AArch32-NEXT: entry:
16131613
// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8
1614-
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10]])
1614+
// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6]])
16151615
// AArch32-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8
1616-
// AArch32-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8
1617-
// AArch32-NEXT: ret double [[TMP2]]
1616+
// AArch32-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8
1617+
// AArch32-NEXT: ret double [[TMP1]]
16181618
//
16191619
// AArch64-LABEL: @test_rsrf64(
16201620
// AArch64-NEXT: entry:
16211621
// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8
1622-
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]])
1622+
// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]])
16231623
// AArch64-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8
1624-
// AArch64-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8
1625-
// AArch64-NEXT: ret double [[TMP2]]
1624+
// AArch64-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8
1625+
// AArch64-NEXT: ret double [[TMP1]]
16261626
//
16271627
double test_rsrf64() {
16281628
#ifdef __ARM_32BIT_STATE
@@ -1636,17 +1636,17 @@ double test_rsrf64() {
16361636
// AArch32-NEXT: entry:
16371637
// AArch32-NEXT: [[V_ADDR:%.*]] = alloca float, align 4
16381638
// AArch32-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4
1639-
// AArch32-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4
1640-
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[TMP1]])
1639+
// AArch32-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4
1640+
// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[TMP0]])
16411641
// AArch32-NEXT: ret void
16421642
//
16431643
// AArch64-LABEL: @test_wsrf(
16441644
// AArch64-NEXT: entry:
16451645
// AArch64-NEXT: [[V_ADDR:%.*]] = alloca float, align 4
16461646
// AArch64-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4
1647-
// AArch64-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4
1648-
// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1649-
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP2]])
1647+
// AArch64-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4
1648+
// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1649+
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP1]])
16501650
// AArch64-NEXT: ret void
16511651
//
16521652
void test_wsrf(float v) {
@@ -1661,16 +1661,16 @@ void test_wsrf(float v) {
16611661
// AArch32-NEXT: entry:
16621662
// AArch32-NEXT: [[V_ADDR:%.*]] = alloca double, align 8
16631663
// AArch32-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8
1664-
// AArch32-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8
1665-
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[TMP1]])
1664+
// AArch32-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8
1665+
// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[TMP0]])
16661666
// AArch32-NEXT: ret void
16671667
//
16681668
// AArch64-LABEL: @test_wsrf64(
16691669
// AArch64-NEXT: entry:
16701670
// AArch64-NEXT: [[V_ADDR:%.*]] = alloca double, align 8
16711671
// AArch64-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8
1672-
// AArch64-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8
1673-
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP1]])
1672+
// AArch64-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8
1673+
// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]])
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// AArch64-NEXT: ret void
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//
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void test_wsrf64(double v) {

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