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[RISCV] Don't custom lower direct fp_extends where possible (#125644)
This avoids lowering scalable fp_extends that don't need multiple extends (i.e. f16->f32, f32->f64) to _vl nodes, but converts them back during DAG preprocessing so we don't need to add any more patterns. Keeping the nodes in their generic SDNode form matches more splat patterns
1 parent 05a09e6 commit 0815b0e

14 files changed

+923
-1481
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,19 @@ void RISCVDAGToDAGISel::PreprocessISelDAG() {
119119
MachineMemOperand::MOLoad);
120120
break;
121121
}
122+
case ISD::FP_EXTEND: {
123+
// We only have vector patterns for riscv_fpextend_vl in isel.
124+
SDLoc DL(N);
125+
MVT VT = N->getSimpleValueType(0);
126+
if (!VT.isVector())
127+
break;
128+
SDValue VLMAX = CurDAG->getRegister(RISCV::X0, Subtarget->getXLenVT());
129+
SDValue TrueMask = CurDAG->getNode(
130+
RISCVISD::VMSET_VL, DL, VT.changeVectorElementType(MVT::i1), VLMAX);
131+
Result = CurDAG->getNode(RISCVISD::FP_EXTEND_VL, DL, VT, N->getOperand(0),
132+
TrueMask, VLMAX);
133+
break;
134+
}
122135
}
123136

124137
if (Result) {

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9060,6 +9060,10 @@ RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
90609060

90619061
bool IsDirectConv = IsDirectExtend || IsDirectTrunc;
90629062

9063+
// We have regular SD node patterns for direct non-VL extends.
9064+
if (VT.isScalableVector() && IsDirectConv && !IsVP)
9065+
return Op;
9066+
90639067
// Prepare any fixed-length vector operands.
90649068
MVT ContainerVT = VT;
90659069
SDValue Mask, VL;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 0 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1412,29 +1412,6 @@ multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_n
14121412
}
14131413
}
14141414

1415-
multiclass VPatWidenReductionVL_RM<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
1416-
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
1417-
defvar vti = vtiToWti.Vti;
1418-
defvar wti = vtiToWti.Wti;
1419-
defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
1420-
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
1421-
GetVTypePredicates<wti>.Predicates) in {
1422-
def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$passthru),
1423-
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1))),
1424-
VR:$rs2, (vti.Mask V0), VLOpFrag,
1425-
(XLenVT timm:$policy))),
1426-
(!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK")
1427-
(wti_m1.Vector VR:$passthru), (vti.Vector vti.RegClass:$rs1),
1428-
(wti_m1.Vector VR:$rs2), (vti.Mask V0),
1429-
// Value to indicate no rounding mode change in
1430-
// RISCVInsertReadWriteCSR
1431-
FRM_DYN,
1432-
GPR:$vl, vti.Log2SEW,
1433-
(XLenVT timm:$policy))>;
1434-
}
1435-
}
1436-
}
1437-
14381415
multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
14391416
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
14401417
defvar vti = vtiToWti.Vti;
@@ -2653,13 +2630,9 @@ defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", is_float=1>;
26532630
defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", is_float=1>;
26542631

26552632
// 14.4. Vector Widening Floating-Point Reduction Instructions
2656-
defm : VPatWidenReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse,
2657-
"PseudoVFWREDOSUM", is_float=1>;
26582633
defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_SEQ_FADD_vl,
26592634
riscv_fpextend_vl_oneuse,
26602635
"PseudoVFWREDOSUM", is_float=1>;
2661-
defm : VPatWidenReductionVL_RM<rvv_vecreduce_FADD_vl, fpext_oneuse,
2662-
"PseudoVFWREDUSUM", is_float=1>;
26632636
defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_FADD_vl,
26642637
riscv_fpextend_vl_oneuse,
26652638
"PseudoVFWREDUSUM", is_float=1>;

‎llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -755,14 +755,12 @@ define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vsca
755755
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
756756
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
757757
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
758-
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
758+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
759759
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
760-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
760+
; ZVFHMIN-NEXT: vmv1r.v v9, v8
761+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
761762
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
762-
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
763-
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
764-
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
765-
; ZVFHMIN-NEXT: vfmax.vv v9, v10, v8
763+
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
766764
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
767765
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
768766
; ZVFHMIN-NEXT: ret
@@ -789,14 +787,12 @@ define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vsca
789787
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
790788
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
791789
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
792-
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
790+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
793791
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
794-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
792+
; ZVFHMIN-NEXT: vmv1r.v v8, v9
793+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
795794
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
796-
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0
797-
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
798-
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
799-
; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
795+
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
800796
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
801797
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
802798
; ZVFHMIN-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll‎

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -755,14 +755,12 @@ define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vsca
755755
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
756756
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
757757
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
758-
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
758+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
759759
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
760-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
760+
; ZVFHMIN-NEXT: vmv1r.v v9, v8
761+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
761762
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
762-
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
763-
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
764-
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
765-
; ZVFHMIN-NEXT: vfmin.vv v9, v10, v8
763+
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
766764
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
767765
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
768766
; ZVFHMIN-NEXT: ret
@@ -789,14 +787,12 @@ define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vsca
789787
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
790788
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
791789
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
792-
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
790+
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
793791
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
794-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
792+
; ZVFHMIN-NEXT: vmv1r.v v8, v9
793+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
795794
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
796-
; ZVFHMIN-NEXT: vmerge.vvm v10, v9, v8, v0
797-
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
798-
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
799-
; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
795+
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
800796
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
801797
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
802798
; ZVFHMIN-NEXT: ret

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