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[CIR][CIRGen][Builtin][Neon] Lower neon_vqshrn_n_v (#1144)
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-49
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2 files changed

+86
-49
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3904,7 +3904,14 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
39043904
SInt32Ty},
39053905
Ops, "aarch64.neon.sqrshrun", ty, getLoc(E->getExprLoc()));
39063906
case NEON::BI__builtin_neon_vqshrn_n_v:
3907-
llvm_unreachable("NEON::BI__builtin_neon_vqshrn_n_v NYI");
3907+
return emitNeonCall(
3908+
builder,
3909+
{builder.getExtendedOrTruncatedElementVectorType(
3910+
vTy, true /* extend */,
3911+
mlir::cast<cir::IntType>(vTy.getEltType()).isSigned()),
3912+
SInt32Ty},
3913+
Ops, usgn ? "aarch64.neon.uqshrn" : "aarch64.neon.sqshrn", ty,
3914+
getLoc(E->getExprLoc()));
39083915
case NEON::BI__builtin_neon_vrshrn_n_v:
39093916
return emitNeonCall(
39103917
builder,

‎clang/test/CIR/CodeGen/AArch64/neon.c‎

Lines changed: 78 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -6926,59 +6926,89 @@ uint32x2_t test_vqrshrun_n_s64(int64x2_t a) {
69266926
// return vqrshrun_high_n_s64(a, b, 19);
69276927
// }
69286928

6929-
// NYI-LABEL: @test_vqshrn_n_s16(
6930-
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
6931-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6932-
// NYI: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6933-
// NYI: ret <8 x i8> [[VQSHRN_N1]]
6934-
// int8x8_t test_vqshrn_n_s16(int16x8_t a) {
6935-
// return vqshrn_n_s16(a, 3);
6936-
// }
6929+
int8x8_t test_vqshrn_n_s16(int16x8_t a) {
6930+
return vqshrn_n_s16(a, 3);
69376931

6938-
// NYI-LABEL: @test_vqshrn_n_s32(
6939-
// NYI: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
6940-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6941-
// NYI: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 19)
6942-
// NYI: ret <4 x i16> [[VQSHRN_N1]]
6943-
// int16x4_t test_vqshrn_n_s32(int32x4_t a) {
6944-
// return vqshrn_n_s32(a, 9);
6945-
// }
6932+
// CIR-LABEL: vqshrn_n_s16
6933+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6934+
// CIR-SAME: (!cir.vector<!s16i x 8>, !s32i) -> !cir.vector<!s8i x 8>
69466935

6947-
// NYI-LABEL: @test_vqshrn_n_s64(
6948-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
6949-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6950-
// NYI: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6951-
// NYI: ret <2 x i32> [[VQSHRN_N1]]
6952-
// int32x2_t test_vqshrn_n_s64(int64x2_t a) {
6953-
// return vqshrn_n_s64(a, 19);
6954-
// }
6936+
// LLVM:{{.*}}test_vqshrn_n_s16(<8 x i16>{{.*}}[[A:%.*]])
6937+
// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
6938+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6939+
// LLVM: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6940+
// LLVM: ret <8 x i8> [[VQSHRN_N1]]
6941+
}
69556942

6956-
// NYI-LABEL: @test_vqshrn_n_u16(
6957-
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
6958-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6959-
// NYI: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6960-
// NYI: ret <8 x i8> [[VQSHRN_N1]]
6961-
// uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {
6962-
// return vqshrn_n_u16(a, 3);
6963-
// }
6943+
int16x4_t test_vqshrn_n_s32(int32x4_t a) {
6944+
return vqshrn_n_s32(a, 9);
69646945

6965-
// NYI-LABEL: @test_vqshrn_n_u32(
6966-
// NYI: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
6967-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6968-
// NYI: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
6969-
// NYI: ret <4 x i16> [[VQSHRN_N1]]
6970-
// uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {
6971-
// return vqshrn_n_u32(a, 9);
6972-
// }
6946+
// CIR-LABEL: vqshrn_n_s32
6947+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6948+
// CIR-SAME: (!cir.vector<!s32i x 4>, !s32i) -> !cir.vector<!s16i x 4>
69736949

6974-
// NYI-LABEL: @test_vqshrn_n_u64(
6975-
// NYI: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
6976-
// NYI: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6977-
// NYI: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6978-
// NYI: ret <2 x i32> [[VQSHRN_N1]]
6979-
// uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {
6980-
// return vqshrn_n_u64(a, 19);
6981-
// }
6950+
// LLVM:{{.*}}test_vqshrn_n_s32(<4 x i32>{{.*}}[[A:%.*]])
6951+
// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
6952+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6953+
// LLVM: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
6954+
// LLVM: ret <4 x i16> [[VQSHRN_N1]]
6955+
}
6956+
6957+
int32x2_t test_vqshrn_n_s64(int64x2_t a) {
6958+
return vqshrn_n_s64(a, 19);
6959+
6960+
// CIR-LABEL: vqshrn_n_s64
6961+
// CIR: cir.llvm.intrinsic "aarch64.neon.sqshrn" {{%.*}}, {{%.*}} :
6962+
// CIR-SAME: (!cir.vector<!s64i x 2>, !s32i) -> !cir.vector<!s32i x 2>
6963+
6964+
// LLVM:{{.*}}test_vqshrn_n_s64(<2 x i64>{{.*}}[[A:%.*]])
6965+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
6966+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
6967+
// LLVM: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
6968+
// LLVM: ret <2 x i32> [[VQSHRN_N1]]
6969+
}
6970+
6971+
uint8x8_t test_vqshrn_n_u16(uint16x8_t a) {
6972+
return vqshrn_n_u16(a, 3);
6973+
6974+
// CIR-LABEL: vqshrn_n_u16
6975+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
6976+
// CIR-SAME: (!cir.vector<!u16i x 8>, !s32i) -> !cir.vector<!u8i x 8>
6977+
6978+
// LLVM:{{.*}}test_vqshrn_n_u16(<8 x i16>{{.*}}[[A:%.*]])
6979+
// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8>
6980+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
6981+
// LLVM: [[VQSHRN_N1:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[VQSHRN_N]], i32 3)
6982+
// LLVM: ret <8 x i8> [[VQSHRN_N1]]
6983+
}
6984+
6985+
uint16x4_t test_vqshrn_n_u32(uint32x4_t a) {
6986+
return vqshrn_n_u32(a, 9);
6987+
6988+
// CIR-LABEL: vqshrn_n_u32
6989+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
6990+
// CIR-SAME: (!cir.vector<!u32i x 4>, !s32i) -> !cir.vector<!u16i x 4>
6991+
6992+
// LLVM:{{.*}}test_vqshrn_n_u32(<4 x i32>{{.*}}[[A:%.*]])
6993+
// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
6994+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
6995+
// LLVM: [[VQSHRN_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[VQSHRN_N]], i32 9)
6996+
// LLVM: ret <4 x i16> [[VQSHRN_N1]]
6997+
}
6998+
6999+
uint32x2_t test_vqshrn_n_u64(uint64x2_t a) {
7000+
return vqshrn_n_u64(a, 19);
7001+
7002+
// CIR-LABEL: vqshrn_n_u64
7003+
// CIR: cir.llvm.intrinsic "aarch64.neon.uqshrn" {{%.*}}, {{%.*}} :
7004+
// CIR-SAME: (!cir.vector<!u64i x 2>, !s32i) -> !cir.vector<!u32i x 2>
7005+
7006+
// LLVM:{{.*}}test_vqshrn_n_u64(<2 x i64>{{.*}}[[A:%.*]])
7007+
// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
7008+
// LLVM: [[VQSHRN_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
7009+
// LLVM: [[VQSHRN_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[VQSHRN_N]], i32 19)
7010+
// LLVM: ret <2 x i32> [[VQSHRN_N1]]
7011+
}
69827012

69837013
// NYI-LABEL: @test_vqshrn_high_n_s16(
69847014
// NYI: [[TMP0:%.*]] = bitcast <8 x i16> %b to <16 x i8>

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