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[CIR][CIRGen][Builtin][Neon] Lower vqdmulhq_lane, vqdmulh_lane, vqrdmulhq_lane and vqrdmulh_lane (#985)
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp‎

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@@ -2280,6 +2280,26 @@ mlir::Value CIRGenFunction::buildCommonNeonBuiltinExpr(
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return builder.createVecShuffle(getLoc(e->getExprLoc()), ops[0], ops[1],
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indices);
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}
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case NEON::BI__builtin_neon_vqdmulhq_lane_v:
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case NEON::BI__builtin_neon_vqdmulh_lane_v:
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case NEON::BI__builtin_neon_vqrdmulhq_lane_v:
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case NEON::BI__builtin_neon_vqrdmulh_lane_v: {
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mlir::cir::VectorType resTy =
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(builtinID == NEON::BI__builtin_neon_vqdmulhq_lane_v ||
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builtinID == NEON::BI__builtin_neon_vqrdmulhq_lane_v)
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? mlir::cir::VectorType::get(builder.getContext(), vTy.getEltType(),
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vTy.getSize() * 2)
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: vTy;
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mlir::cir::VectorType mulVecT =
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GetNeonType(this, NeonTypeFlags(neonType.getEltType(), false,
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/*isQuad*/ false));
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return buildNeonCall(builder, {resTy, mulVecT, SInt32Ty}, ops,
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(builtinID == NEON::BI__builtin_neon_vqdmulhq_lane_v ||
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builtinID == NEON::BI__builtin_neon_vqdmulh_lane_v)
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? "llvm.aarch64.neon.sqdmulh.lane"
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: "llvm.aarch64.neon.sqrdmulh.lane",
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resTy, getLoc(e->getExprLoc()));
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}
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}
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// This second switch is for the intrinsics that might have a more generic

‎clang/test/CIR/CodeGen/AArch64/neon-arith.c‎

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@@ -218,3 +218,116 @@ float64x2_t test_vpaddq_f64(float64x2_t a, float64x2_t b) {
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// LLVM: {{.*}}test_vpaddq_f64(<2 x double>{{.*}}[[A:%.*]], <2 x double>{{.*}}[[B:%.*]])
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// LLVM: [[RES:%.*]] = call <2 x double> @llvm.aarch64.neon.faddp.v2f64(<2 x double> [[A]], <2 x double> [[B]])
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// LLVM: ret <2 x double> [[RES]]
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int16x4_t test_vqdmulh_lane_s16(int16x4_t a, int16x4_t v) {
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return vqdmulh_lane_s16(a, v, 3);
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}
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// CIR-LABEL: vqdmulh_lane_s16
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// CIR: [[LANE:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR: (!cir.vector<!s16i x 4>, !cir.vector<!s16i x 4>, !s32i) -> !cir.vector<!s16i x 4>
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// LLVM: {{.*}}test_vqdmulh_lane_s16(<4 x i16>{{.*}}[[A:%.*]], <4 x i16>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.lane.v4i16.v4i16
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// LLVM-SAME: (<4 x i16> [[A]], <4 x i16> [[V]], i32 3)
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// LLVM: ret <4 x i16> [[RES]]
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int32x2_t test_vqdmulh_lane_s32(int32x2_t a, int32x2_t v) {
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return vqdmulh_lane_s32(a, v, 1);
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}
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// CIR-LABEL: vqdmulh_lane_s32
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// CIR: [[LANE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR: (!cir.vector<!s32i x 2>, !cir.vector<!s32i x 2>, !s32i) -> !cir.vector<!s32i x 2>
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// LLVM: {{.*}}test_vqdmulh_lane_s32(<2 x i32>{{.*}}[[A:%.*]], <2 x i32>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.lane.v2i32.v2i32
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// LLVM-SAME: (<2 x i32> [[A]], <2 x i32> [[V]], i32 1)
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// LLVM: ret <2 x i32> [[RES]]
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int16x8_t test_vqdmulhq_lane_s16(int16x8_t a, int16x4_t v) {
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return vqdmulhq_lane_s16(a, v, 3);
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}
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// CIR-LABEL: vqdmulhq_lane_s16
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// CIR: [[LANE:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR: (!cir.vector<!s16i x 8>, !cir.vector<!s16i x 4>, !s32i) -> !cir.vector<!s16i x 8>
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// LLVM: {{.*}}test_vqdmulhq_lane_s16(<8 x i16>{{.*}}[[A:%.*]], <4 x i16>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.lane.v8i16.v4i16
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// LLVM-SAME: (<8 x i16> [[A]], <4 x i16> [[V]], i32 3)
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// LLVM: ret <8 x i16> [[RES]]
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int32x4_t test_vqdmulhq_lane_s32(int32x4_t a, int32x2_t v) {
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return vqdmulhq_lane_s32(a, v, 1);
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}
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// CIR-LABEL: vqdmulhq_lane_s32
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// CIR: [[LANE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR: (!cir.vector<!s32i x 4>, !cir.vector<!s32i x 2>, !s32i) -> !cir.vector<!s32i x 4>
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// LLVM: {{.*}}test_vqdmulhq_lane_s32(<4 x i32>{{.*}}[[A:%.*]], <2 x i32>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.lane.v4i32.v2i32
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// LLVM-SAME: (<4 x i32> [[A]], <2 x i32> [[V]], i32 1)
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// LLVM: ret <4 x i32> [[RES]]
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int16x4_t test_vqrdmulh_lane_s16(int16x4_t a, int16x4_t v) {
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return vqrdmulh_lane_s16(a, v, 3);
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}
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// CIR-LABEL: vqrdmulh_lane_s16
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// CIR: [[LANE:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR-SAME: (!cir.vector<!s16i x 4>, !cir.vector<!s16i x 4>, !s32i) -> !cir.vector<!s16i x 4>
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// LLVM: {{.*}}test_vqrdmulh_lane_s16(<4 x i16>{{.*}}[[A:%.*]], <4 x i16>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.lane.v4i16.v4i16
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// LLVM-SAME: (<4 x i16> [[A]], <4 x i16> [[V]], i32 3)
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// LLVM: ret <4 x i16> [[RES]]
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int16x8_t test_vqrdmulhq_lane_s16(int16x8_t a, int16x4_t v) {
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return vqrdmulhq_lane_s16(a, v, 3);
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}
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// CIR-LABEL: vqrdmulhq_lane_s16
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// CIR: [[LANE:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR-SAME: (!cir.vector<!s16i x 8>, !cir.vector<!s16i x 4>, !s32i) -> !cir.vector<!s16i x 8>
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// LLVM: {{.*}}test_vqrdmulhq_lane_s16(<8 x i16>{{.*}}[[A:%.*]], <4 x i16>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.lane.v8i16.v4i16
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// LLVM-SAME: (<8 x i16> [[A]], <4 x i16> [[V]], i32 3)
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// LLVM: ret <8 x i16> [[RES]]
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int32x2_t test_vqrdmulh_lane_s32(int32x2_t a, int32x2_t v) {
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return vqrdmulh_lane_s32(a, v, 1);
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}
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// CIR-LABEL: vqrdmulh_lane_s32
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// CIR: [[LANE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR-SAME: (!cir.vector<!s32i x 2>, !cir.vector<!s32i x 2>, !s32i) -> !cir.vector<!s32i x 2>
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// LLVM: {{.*}}test_vqrdmulh_lane_s32(<2 x i32>{{.*}}[[A:%.*]], <2 x i32>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.lane.v2i32.v2i32
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// LLVM-SAME: (<2 x i32> [[A]], <2 x i32> [[V]], i32 1)
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// LLVM: ret <2 x i32> [[RES]]
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int32x4_t test_vqrdmulhq_lane_s32(int32x4_t a, int32x2_t v) {
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return vqrdmulhq_lane_s32(a, v, 1);
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}
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// CIR-LABEL: vqrdmulhq_lane_s32
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// CIR: [[LANE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: {{%.*}} = cir.llvm.intrinsic "llvm.aarch64.neon.sqrdmulh.lane" {{%.*}}, {{%.*}}, [[LANE]] :
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// CIR-SAME: (!cir.vector<!s32i x 4>, !cir.vector<!s32i x 2>, !s32i) -> !cir.vector<!s32i x 4>
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// LLVM: {{.*}}test_vqrdmulhq_lane_s32(<4 x i32>{{.*}}[[A:%.*]], <2 x i32>{{.*}}[[V:%.*]])
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// LLVM: [[RES:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.lane.v4i32.v2i32
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// LLVM-SAME: (<4 x i32> [[A]], <2 x i32> [[V]], i32 1)
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// LLVM: ret <4 x i32> [[RES]]

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