Support RISC-V

Patch by PkmX.

This patch makes lld recognize RISC-V target and implements basic
relocation for RV32/RV64 (and RVC). This should be necessary for static
linking ELF applications.

The ABI documentation for RISC-V can be found at:
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md.
Note that the documentation is far from complete so we had to figure out
some details from bfd.

The patch should be pretty straightforward. Some highlights:

 - A new relocation Expr R_RISCV_PC_INDIRECT is added. This is needed as
   the low part of a PC-relative relocation is linked to the corresponding
   high part (auipc), see:
   https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses

 - LLVM's MC support for RISC-V is very incomplete (we are working on
   this), so tests are given in objectyaml format with the original
   assembly included in the comments. Once we have complete support for
   RISC-V in MC, we can switch to llvm-as/llvm-objdump.

 - We don't support linker relaxation for now as it requires greater
   changes to lld that is beyond the scope of this patch. Once this is
   accepted we can start to work on adding relaxation to lld.

Differential Revision: https://reviews.llvm.org/D39322

git-svn-id: https://llvm.org/svn/llvm-project/lld/trunk@339364 91177308-0d34-0410-b5e6-96231b3b80d8

Author: rui314

ELF/Arch/RISCV.cpp

@@ -0,0 +1,277 @@
+//===- RISCV.cpp ----------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Target.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+
+class RISCV final : public TargetInfo {
+public:
+  virtual uint32_t calcEFlags() const override;
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+
+} // end anonymous namespace
+
+static uint32_t getEFlags(InputFile *F) {
+  if (Config->Is64)
+    return cast<ObjFile<ELF64LE>>(F)->getObj().getHeader()->e_flags;
+  else
+    return cast<ObjFile<ELF32LE>>(F)->getObj().getHeader()->e_flags;
+}
+
+uint32_t RISCV::calcEFlags() const {
+  assert(!ObjectFiles.empty());
+
+  uint32_t Target = getEFlags(ObjectFiles.front());
+
+  for (InputFile *F : ObjectFiles) {
+    uint32_t EFlags = getEFlags(F);
+    if (EFlags & EF_RISCV_RVC)
+      Target |= EF_RISCV_RVC;
+
+    if ((EFlags & EF_RISCV_FLOAT_ABI) != (Target & EF_RISCV_FLOAT_ABI))
+      error(toString(F) +
+            ": cannot link object files with different floating-point ABI");
+
+    if ((EFlags & EF_RISCV_RVE) != (Target & EF_RISCV_RVE))
+      error(toString(F) +
+            ": cannot link object files with different EF_RISCV_RVE");
+  }
+
+  return Target;
+}
+
+RelExpr RISCV::getRelExpr(const RelType Type, const Symbol &S,
+                          const uint8_t *Loc) const {
+  switch (Type) {
+  case R_RISCV_JAL:
+  case R_RISCV_BRANCH:
+  case R_RISCV_CALL:
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_RVC_BRANCH:
+  case R_RISCV_RVC_JUMP:
+  case R_RISCV_32_PCREL:
+    return R_PC;
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_PCREL_LO12_S:
+    return R_RISCV_PC_INDIRECT;
+  case R_RISCV_RELAX:
+  case R_RISCV_ALIGN:
+    return R_HINT;
+  default:
+    return R_ABS;
+  }
+}
+
+// Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
+static uint32_t extractBits(uint64_t V, uint32_t Begin, uint32_t End) {
+  return (V & ((1ULL << (Begin + 1)) - 1)) >> End;
+}
+
+void RISCV::relocateOne(uint8_t *Loc, const RelType Type,
+                        const uint64_t Val) const {
+  switch (Type) {
+  case R_RISCV_32:
+    write32le(Loc, Val);
+    return;
+  case R_RISCV_64:
+    write64le(Loc, Val);
+    return;
+
+  case R_RISCV_RVC_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 8, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE383;
+    uint16_t Imm8 = extractBits(Val, 8, 8) << 12;
+    uint16_t Imm4_3 = extractBits(Val, 4, 3) << 10;
+    uint16_t Imm7_6 = extractBits(Val, 7, 6) << 5;
+    uint16_t Imm2_1 = extractBits(Val, 2, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm8 | Imm4_3 | Imm7_6 | Imm2_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_JUMP: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 11, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE003;
+    uint16_t Imm11 = extractBits(Val, 11, 11) << 12;
+    uint16_t Imm4 = extractBits(Val, 4, 4) << 11;
+    uint16_t Imm9_8 = extractBits(Val, 9, 8) << 9;
+    uint16_t Imm10 = extractBits(Val, 10, 10) << 8;
+    uint16_t Imm6 = extractBits(Val, 6, 6) << 7;
+    uint16_t Imm7 = extractBits(Val, 7, 7) << 6;
+    uint16_t Imm3_1 = extractBits(Val, 3, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm11 | Imm4 | Imm9_8 | Imm10 | Imm6 | Imm7 | Imm3_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_LUI: {
+    int32_t Imm = ((Val + 0x800) >> 12);
+    checkUInt(Loc, Imm, 6, Type);
+    if (Imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
+      write16le(Loc, (read16le(Loc) & 0x0F83) | 0x4000);
+    } else {
+      uint16_t Imm17 = extractBits(Val + 0x800, 17, 17) << 12;
+      uint16_t Imm16_12 = extractBits(Val + 0x800, 16, 12) << 2;
+      write16le(Loc, (read16le(Loc) & 0xEF83) | Imm17 | Imm16_12);
+    }
+    return;
+  }
+
+  case R_RISCV_JAL: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 20, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0xFFF;
+    uint32_t Imm20 = extractBits(Val, 20, 20) << 31;
+    uint32_t Imm10_1 = extractBits(Val, 10, 1) << 21;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 20;
+    uint32_t Imm19_12 = extractBits(Val, 19, 12) << 12;
+    Insn |= Imm20 | Imm10_1 | Imm11 | Imm19_12;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 12, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0x1FFF07F;
+    uint32_t Imm12 = extractBits(Val, 12, 12) << 31;
+    uint32_t Imm10_5 = extractBits(Val, 10, 5) << 25;
+    uint32_t Imm4_1 = extractBits(Val, 4, 1) << 8;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 7;
+    Insn |= Imm12 | Imm10_5 | Imm4_1 | Imm11;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  // auipc + jalr pair
+  case R_RISCV_CALL: {
+    checkInt(Loc, Val, 32, Type);
+    if (isInt<32>(Val)) {
+      relocateOne(Loc, R_RISCV_PCREL_HI20, Val);
+      relocateOne(Loc + 4, R_RISCV_PCREL_LO12_I, Val);
+    }
+    return;
+  }
+
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_HI20: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    write32le(Loc, (read32le(Loc) & 0xFFF) | (Hi & 0xFFFFF000));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_LO12_I: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    write32le(Loc, (read32le(Loc) & 0xFFFFF) | ((Lo & 0xFFF) << 20));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_S:
+  case R_RISCV_LO12_S: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    uint32_t Imm11_5 = extractBits(Lo, 11, 5) << 25;
+    uint32_t Imm4_0 = extractBits(Lo, 4, 0) << 7;
+    write32le(Loc, (read32le(Loc) & 0x1FFF07F) | Imm11_5 | Imm4_0);
+    return;
+  }
+
+  case R_RISCV_ADD8:
+    *Loc += Val;
+    return;
+  case R_RISCV_ADD16:
+    write16le(Loc, read16le(Loc) + Val);
+    return;
+  case R_RISCV_ADD32:
+    write32le(Loc, read32le(Loc) + Val);
+    return;
+  case R_RISCV_ADD64:
+    write64le(Loc, read64le(Loc) + Val);
+    return;
+  case R_RISCV_SUB6:
+    *Loc = (*Loc & 0xc0) | (((*Loc & 0x3f) - Val) & 0x3f);
+    return;
+  case R_RISCV_SUB8:
+    *Loc -= Val;
+    return;
+  case R_RISCV_SUB16:
+    write16le(Loc, read16le(Loc) - Val);
+    return;
+  case R_RISCV_SUB32:
+    write32le(Loc, read32le(Loc) - Val);
+    return;
+  case R_RISCV_SUB64:
+    write64le(Loc, read64le(Loc) - Val);
+    return;
+  case R_RISCV_SET6:
+    *Loc = (*Loc & 0xc0) | (Val & 0x3f);
+    return;
+  case R_RISCV_SET8:
+    *Loc = Val;
+    return;
+  case R_RISCV_SET16:
+    write16le(Loc, Val);
+    return;
+  case R_RISCV_SET32:
+  case R_RISCV_32_PCREL:
+    write32le(Loc, Val);
+    return;
+
+  case R_RISCV_ALIGN:
+  case R_RISCV_RELAX:
+    return; // Ignored (for now)
+  case R_RISCV_NONE:
+    return; // Do nothing
+
+  // These are handled by the dynamic linker
+  case R_RISCV_RELATIVE:
+  case R_RISCV_COPY:
+  case R_RISCV_JUMP_SLOT:
+  // GP-relative relocations are only produced after relaxation, which
+  // we don't support for now
+  case R_RISCV_GPREL_I:
+  case R_RISCV_GPREL_S:
+  default:
+    error(getErrorLocation(Loc) +
+          "unimplemented relocation: " + toString(Type));
+    return;
+  }
+}
+
+TargetInfo *elf::getRISCVTargetInfo() {
+  static RISCV Target;
+  return &Target;
+}

ELF/CMakeLists.txt

@@ -17,6 +17,7 @@ add_lld_library(lldELF
   Arch/MipsArchTree.cpp
   Arch/PPC.cpp
   Arch/PPC64.cpp
+  Arch/RISCV.cpp
   Arch/SPARCV9.cpp
   Arch/X86.cpp
   Arch/X86_64.cpp

ELF/Driver.cpp

@@ -125,9 +125,11 @@ static std::tuple<ELFKind, uint16_t, uint8_t> parseEmulation(StringRef Emul) {
           .Case("elf32_x86_64", {ELF32LEKind, EM_X86_64})
           .Cases("elf32btsmip", "elf32btsmipn32", {ELF32BEKind, EM_MIPS})
           .Cases("elf32ltsmip", "elf32ltsmipn32", {ELF32LEKind, EM_MIPS})
+          .Case("elf32lriscv", {ELF32LEKind, EM_RISCV})
           .Case("elf32ppc", {ELF32BEKind, EM_PPC})
           .Case("elf64btsmip", {ELF64BEKind, EM_MIPS})
           .Case("elf64ltsmip", {ELF64LEKind, EM_MIPS})
+          .Case("elf64lriscv", {ELF64LEKind, EM_RISCV})
           .Case("elf64ppc", {ELF64BEKind, EM_PPC64})
           .Case("elf64lppc", {ELF64LEKind, EM_PPC64})
           .Cases("elf_amd64", "elf_x86_64", {ELF64LEKind, EM_X86_64})
@@ -986,7 +988,8 @@ static void setConfigs(opt::InputArgList &Args) {
   // ABI defines which one you need to use. The following expression expresses
   // that.
   Config->IsRela =
-      (Config->Is64 || IsX32 || Machine == EM_PPC) && Machine != EM_MIPS;
+      (Config->Is64 || IsX32 || Machine == EM_PPC || Machine == EM_RISCV) &&
+      Machine != EM_MIPS;
 
   // If the output uses REL relocations we must store the dynamic relocation
   // addends to the output sections. We also store addends for RELA relocations

ELF/InputSection.cpp

@@ -481,6 +481,33 @@ static uint64_t getARMStaticBase(const Symbol &Sym) {
   return OS->PtLoad->FirstSec->Addr;
 }
 
+// For R_RISCV_PC_INDIRECT (R_RISCV_PCREL_LO12_{I,S}), the symbol actually
+// points the corresponding R_RISCV_PCREL_HI20 relocation, and the target VA
+// is calculated using PCREL_HI20's symbol.
+//
+// This function returns the R_RISCV_PCREL_HI20 relocation from
+// R_RISCV_PCREL_LO12's symbol and addend.
+Relocation *lld::elf::getRISCVPCRelHi20(const Symbol *Sym, uint64_t Addend) {
+  const Defined *D = cast<Defined>(Sym);
+  InputSection *IS = cast<InputSection>(D->Section);
+
+  if (Addend != 0)
+    warn("Non-zero addend in R_RISCV_PCREL_LO12 relocation to " +
+         IS->getObjMsg(D->Value) + " is ignored");
+
+  // Relocations are sorted by offset, so we can use std::equal_range to do
+  // binary search.
+  auto Range = std::equal_range(IS->Relocations.begin(), IS->Relocations.end(),
+                                D->Value, RelocationOffsetComparator{});
+  for (auto It = std::get<0>(Range); It != std::get<1>(Range); ++It)
+    if (isRelExprOneOf<R_PC>(It->Expr))
+      return &*It;
+
+  error("R_RISCV_PCREL_LO12 relocation points to " + IS->getObjMsg(D->Value) +
+        " without an associated R_RISCV_PCREL_HI20 relocation");
+  return nullptr;
+}
+
 static uint64_t getRelocTargetVA(const InputFile *File, RelType Type, int64_t A,
                                  uint64_t P, const Symbol &Sym, RelExpr Expr) {
   switch (Expr) {
@@ -567,6 +594,13 @@ static uint64_t getRelocTargetVA(const InputFile *File, RelType Type, int64_t A,
       Dest = getAArch64Page(Sym.getVA(A));
     return Dest - getAArch64Page(P);
   }
+  case R_RISCV_PC_INDIRECT: {
+    const Relocation *HiRel = getRISCVPCRelHi20(&Sym, A);
+    if (!HiRel)
+      return 0;
+    return getRelocTargetVA(File, HiRel->Type, HiRel->Addend, Sym.getVA(),
+                            *HiRel->Sym, HiRel->Expr);
+  }
   case R_PC: {
     uint64_t Dest;
     if (Sym.isUndefWeak()) {

ELF/InputSection.h

@@ -353,6 +353,8 @@ class InputSection : public InputSectionBase {
 
 // The list of all input sections.
 extern std::vector<InputSectionBase *> InputSections;
+
+Relocation *getRISCVPCRelHi20(const Symbol *Sym, const uint64_t Addend);
 } // namespace elf
 
 std::string toString(const elf::InputSectionBase *);

ELF/Relocations.cpp

@@ -1047,6 +1047,11 @@ static void scanRelocs(InputSectionBase &Sec, ArrayRef<RelTy> Rels) {
 
   for (auto I = Rels.begin(), End = Rels.end(); I != End;)
     scanReloc<ELFT>(Sec, GetOffset, I, End);
+
+  // Sort relocations by offset to binary search for R_RISCV_PCREL_HI20
+  if (Config->EMachine == EM_RISCV)
+    std::stable_sort(Sec.Relocations.begin(), Sec.Relocations.end(),
+                     RelocationOffsetComparator{});
 }
 
 template <class ELFT> void elf::scanRelocations(InputSectionBase &S) {