Verify intrinsics don't leak to i686 (rust-lang#305)

Some intrinsics take `i64` or `u64` arguments which typically means that they're
using 64-bit registers and aren't actually available on x86. This commit adds a
check to stdsimd-verify to assert this and moves around some intrinsics that I
believe should only be available on x86_64.

This commit was checked in many places against gcc/clang/MSVC using godbolt.org
to ensure that we're agreeing with what other compilers are doing.

Closes rust-lang#304

Author: alexcrichton

coresimd/src/x86/i586/abm.rs

@@ -30,16 +30,6 @@ pub unsafe fn _lzcnt_u32(x: u32) -> u32 {
     x.leading_zeros()
 }
 
-/// Counts the leading most significant zero bits.
-///
-/// When the operand is zero, it returns its size in bits.
-#[inline(always)]
-#[target_feature(enable = "lzcnt")]
-#[cfg_attr(test, assert_instr(lzcnt))]
-pub unsafe fn _lzcnt_u64(x: u64) -> u64 {
-    x.leading_zeros() as u64
-}
-
 /// Counts the bits that are set.
 #[inline(always)]
 #[target_feature(enable = "popcnt")]
@@ -48,14 +38,6 @@ pub unsafe fn _popcnt32(x: i32) -> i32 {
     x.count_ones() as i32
 }
 
-/// Counts the bits that are set.
-#[inline(always)]
-#[target_feature(enable = "popcnt")]
-#[cfg_attr(test, assert_instr(popcnt))]
-pub unsafe fn _popcnt64(x: i64) -> i32 {
-    x.count_ones() as i32
-}
-
 #[cfg(test)]
 mod tests {
     use stdsimd_test::simd_test;
@@ -67,18 +49,8 @@ mod tests {
         assert_eq!(abm::_lzcnt_u32(0b0101_1010), 25);
     }
 
-    #[simd_test = "lzcnt"]
-    unsafe fn _lzcnt_u64() {
-        assert_eq!(abm::_lzcnt_u64(0b0101_1010), 57);
-    }
-
     #[simd_test = "popcnt"]
     unsafe fn _popcnt32() {
         assert_eq!(abm::_popcnt32(0b0101_1010), 4);
     }
-
-    #[simd_test = "popcnt"]
-    unsafe fn _popcnt64() {
-        assert_eq!(abm::_popcnt64(0b0101_1010), 4);
-    }
 }

coresimd/src/x86/i586/avx.rs

@@ -1245,15 +1245,6 @@ pub unsafe fn _mm256_insert_epi32(a: __m256i, i: i32, index: i32) -> __m256i {
     mem::transmute(simd_insert(a.as_i32x8(), (index as u32) & 7, i))
 }
 
-/// Copy `a` to result, and insert the 64-bit integer `i` into result
-/// at the location specified by `index`.
-#[inline(always)]
-#[target_feature(enable = "avx")]
-// This intrinsic has no corresponding instruction.
-pub unsafe fn _mm256_insert_epi64(a: __m256i, i: i64, index: i32) -> __m256i {
-    mem::transmute(simd_insert(a.as_i64x4(), (index as u32) & 3, i))
-}
-
 /// Load 256-bits (composed of 4 packed double-precision (64-bit)
 /// floating-point elements) from memory into result.
 /// `mem_addr` must be aligned on a 32-byte boundary or a
@@ -3307,14 +3298,6 @@ mod tests {
         assert_eq_m256i(r, e);
     }
 
-    #[simd_test = "avx"]
-    unsafe fn test_mm256_insert_epi64() {
-        let a = _mm256_setr_epi64x(1, 2, 3, 4);
-        let r = _mm256_insert_epi64(a, 0, 3);
-        let e = _mm256_setr_epi64x(1, 2, 3, 0);
-        assert_eq_m256i(r, e);
-    }
-
     #[simd_test = "avx"]
     unsafe fn test_mm256_load_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);

coresimd/src/x86/i586/avx2.rs

@@ -2887,15 +2887,6 @@ pub unsafe fn _mm256_extract_epi32(a: __m256i, imm8: i32) -> i32 {
     simd_extract(a.as_i32x8(), imm8)
 }
 
-/// Extract a 64-bit integer from `a`, selected with `imm8`.
-#[inline(always)]
-#[target_feature(enable = "avx2")]
-// This intrinsic has no corresponding instruction.
-pub unsafe fn _mm256_extract_epi64(a: __m256i, imm8: i32) -> i64 {
-    let imm8 = (imm8 & 3) as u32;
-    simd_extract(a.as_i64x4(), imm8)
-}
-
 /// Returns the first element of the input vector of [4 x double].
 #[inline(always)]
 #[target_feature(enable = "avx2")]
@@ -5246,13 +5237,6 @@ mod tests {
         assert_eq!(r2, 3);
     }
 
-    #[simd_test = "avx2"]
-    unsafe fn test_mm256_extract_epi64() {
-        let a = _mm256_setr_epi64x(0, 1, 2, 3);
-        let r = _mm256_extract_epi64(a, 3);
-        assert_eq!(r, 3);
-    }
-
     #[simd_test = "avx2"]
     unsafe fn test_mm256_cvtsd_f64() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);

coresimd/src/x86/i586/bmi.rs

@@ -21,16 +21,6 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
     _bextr2_u32(a, (start & 0xff_u32) | ((len & 0xff_u32) << 8_u32))
 }
 
-/// Extracts bits in range [`start`, `start` + `length`) from `a` into
-/// the least significant bits of the result.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(bextr))]
-#[cfg(not(target_arch = "x86"))]
-pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
-    _bextr2_u64(a, ((start & 0xff) | ((len & 0xff) << 8)) as u64)
-}
-
 /// Extracts bits of `a` specified by `control` into
 /// the least significant bits of the result.
 ///
@@ -43,19 +33,6 @@ pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 {
     x86_bmi_bextr_32(a, control)
 }
 
-/// Extracts bits of `a` specified by `control` into
-/// the least significant bits of the result.
-///
-/// Bits [7,0] of `control` specify the index to the first bit in the range to
-/// be extracted, and bits [15,8] specify the length of the range.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(bextr))]
-#[cfg(not(target_arch = "x86"))]
-pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
-    x86_bmi_bextr_64(a, control)
-}
-
 /// Bitwise logical `AND` of inverted `a` with `b`.
 #[inline(always)]
 #[target_feature(enable = "bmi")]
@@ -64,14 +41,6 @@ pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 {
     !a & b
 }
 
-/// Bitwise logical `AND` of inverted `a` with `b`.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(andn))]
-pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 {
-    !a & b
-}
-
 /// Extract lowest set isolated bit.
 #[inline(always)]
 #[target_feature(enable = "bmi")]
@@ -80,15 +49,6 @@ pub unsafe fn _blsi_u32(x: u32) -> u32 {
     x & x.wrapping_neg()
 }
 
-/// Extract lowest set isolated bit.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(blsi))]
-#[cfg(not(target_arch = "x86"))] // generates lots of instructions
-pub unsafe fn _blsi_u64(x: u64) -> u64 {
-    x & x.wrapping_neg()
-}
-
 /// Get mask up to lowest set bit.
 #[inline(always)]
 #[target_feature(enable = "bmi")]
@@ -97,15 +57,6 @@ pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
     x ^ (x.wrapping_sub(1_u32))
 }
 
-/// Get mask up to lowest set bit.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(blsmsk))]
-#[cfg(not(target_arch = "x86"))] // generates lots of instructions
-pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
-    x ^ (x.wrapping_sub(1_u64))
-}
-
 /// Resets the lowest set bit of `x`.
 ///
 /// If `x` is sets CF.
@@ -116,17 +67,6 @@ pub unsafe fn _blsr_u32(x: u32) -> u32 {
     x & (x.wrapping_sub(1))
 }
 
-/// Resets the lowest set bit of `x`.
-///
-/// If `x` is sets CF.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(blsr))]
-#[cfg(not(target_arch = "x86"))] // generates lots of instructions
-pub unsafe fn _blsr_u64(x: u64) -> u64 {
-    x & (x.wrapping_sub(1))
-}
-
 /// Counts the number of trailing least significant zero bits.
 ///
 /// When the source operand is 0, it returns its size in bits.
@@ -137,16 +77,6 @@ pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
     x.trailing_zeros()
 }
 
-/// Counts the number of trailing least significant zero bits.
-///
-/// When the source operand is 0, it returns its size in bits.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(tzcnt))]
-pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
-    x.trailing_zeros() as u64
-}
-
 /// Counts the number of trailing least significant zero bits.
 ///
 /// When the source operand is 0, it returns its size in bits.
@@ -157,22 +87,9 @@ pub unsafe fn _mm_tzcnt_32(x: u32) -> i32 {
     x.trailing_zeros() as i32
 }
 
-/// Counts the number of trailing least significant zero bits.
-///
-/// When the source operand is 0, it returns its size in bits.
-#[inline(always)]
-#[target_feature(enable = "bmi")]
-#[cfg_attr(test, assert_instr(tzcnt))]
-pub unsafe fn _mm_tzcnt_64(x: u64) -> i64 {
-    x.trailing_zeros() as i64
-}
-
-#[allow(dead_code)]
 extern "C" {
     #[link_name = "llvm.x86.bmi.bextr.32"]
     fn x86_bmi_bextr_32(x: u32, y: u32) -> u32;
-    #[link_name = "llvm.x86.bmi.bextr.64"]
-    fn x86_bmi_bextr_64(x: u64, y: u64) -> u64;
 }
 
 #[cfg(test)]
@@ -187,13 +104,6 @@ mod tests {
         assert_eq!(r, 0b0000_0101u32);
     }
 
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _bextr_u64() {
-        let r = bmi::_bextr_u64(0b0101_0000u64, 4, 4);
-        assert_eq!(r, 0b0000_0101u64);
-    }
-
     #[simd_test = "bmi"]
     unsafe fn _andn_u32() {
         assert_eq!(bmi::_andn_u32(0, 0), 0);
@@ -217,81 +127,28 @@ mod tests {
         assert_eq!(r, 0b0001_1101u32);
     }
 
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _andn_u64() {
-        assert_eq!(bmi::_andn_u64(0, 0), 0);
-        assert_eq!(bmi::_andn_u64(0, 1), 1);
-        assert_eq!(bmi::_andn_u64(1, 0), 0);
-        assert_eq!(bmi::_andn_u64(1, 1), 0);
-
-        let r = bmi::_andn_u64(0b0000_0000u64, 0b0000_0000u64);
-        assert_eq!(r, 0b0000_0000u64);
-
-        let r = bmi::_andn_u64(0b0000_0000u64, 0b1111_1111u64);
-        assert_eq!(r, 0b1111_1111u64);
-
-        let r = bmi::_andn_u64(0b1111_1111u64, 0b0000_0000u64);
-        assert_eq!(r, 0b0000_0000u64);
-
-        let r = bmi::_andn_u64(0b1111_1111u64, 0b1111_1111u64);
-        assert_eq!(r, 0b0000_0000u64);
-
-        let r = bmi::_andn_u64(0b0100_0000u64, 0b0101_1101u64);
-        assert_eq!(r, 0b0001_1101u64);
-    }
-
     #[simd_test = "bmi"]
     unsafe fn _blsi_u32() {
         assert_eq!(bmi::_blsi_u32(0b1101_0000u32), 0b0001_0000u32);
     }
 
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _blsi_u64() {
-        assert_eq!(bmi::_blsi_u64(0b1101_0000u64), 0b0001_0000u64);
-    }
-
     #[simd_test = "bmi"]
     unsafe fn _blsmsk_u32() {
         let r = bmi::_blsmsk_u32(0b0011_0000u32);
         assert_eq!(r, 0b0001_1111u32);
     }
 
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _blsmsk_u64() {
-        let r = bmi::_blsmsk_u64(0b0011_0000u64);
-        assert_eq!(r, 0b0001_1111u64);
-    }
-
     #[simd_test = "bmi"]
     unsafe fn _blsr_u32() {
         // TODO: test the behavior when the input is 0
         let r = bmi::_blsr_u32(0b0011_0000u32);
         assert_eq!(r, 0b0010_0000u32);
     }
 
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _blsr_u64() {
-        // TODO: test the behavior when the input is 0
-        let r = bmi::_blsr_u64(0b0011_0000u64);
-        assert_eq!(r, 0b0010_0000u64);
-    }
-
     #[simd_test = "bmi"]
     unsafe fn _tzcnt_u32() {
         assert_eq!(bmi::_tzcnt_u32(0b0000_0001u32), 0u32);
         assert_eq!(bmi::_tzcnt_u32(0b0000_0000u32), 32u32);
         assert_eq!(bmi::_tzcnt_u32(0b1001_0000u32), 4u32);
     }
-
-    #[simd_test = "bmi"]
-    #[cfg(not(target_arch = "x86"))]
-    unsafe fn _tzcnt_u64() {
-        assert_eq!(bmi::_tzcnt_u64(0b0000_0001u64), 0u64);
-        assert_eq!(bmi::_tzcnt_u64(0b0000_0000u64), 64u64);
-        assert_eq!(bmi::_tzcnt_u64(0b1001_0000u64), 4u64);
-    }
 }