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[Z80] Add registers definition I, R, MB #1

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Merged
merged 2 commits into from
Jan 31, 2022
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[Z80] Add registers definition I, R, MB #1

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8ffd664
[Z80] Add registers definition I, R, MB
b-s-a Nov 27, 2019
c5383e6
Fix #1.
jacobly0 Jan 31, 2022
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11 changes: 6 additions & 5 deletions llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,7 @@ const TargetRegisterClass *
Z80InstructionSelector::getRegClass(Register Reg,
MachineRegisterInfo &MRI) const {
if (Reg.isPhysical()) {
for (auto *RC : {&Z80::R8RegClass, &Z80::F8RegClass, &Z80::R16RegClass,
for (auto *RC : {&Z80::R8RegClass, &Z80::Z8RegClass, &Z80::R16RegClass,
&Z80::Z16RegClass, &Z80::R24RegClass, &Z80::Z24RegClass})
if (RC->contains(Reg))
return RC;
Expand Down Expand Up @@ -226,8 +226,9 @@ bool Z80InstructionSelector::selectCopy(MachineInstr &I,
if (DstReg.isPhysical()) {
assert(I.isCopy() && "Generic operators do not allow physical registers");

if (DstReg == Z80::F &&
!RBI.constrainGenericRegister(SrcReg, Z80::F8RegClass, MRI))
if ((DstReg == Z80::F || DstReg == Z80::I || DstReg == Z80::R ||
DstReg == Z80::MB) &&
!RBI.constrainGenericRegister(SrcReg, Z80::Z8RegClass, MRI))
return false;

if (DstSize > SrcSize && SrcRegBank.getID() == Z80::GPRRegBankID &&
Expand Down Expand Up @@ -1226,8 +1227,8 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
CallLowering::ArgInfo::NoArgIndex);
createLibcall(MIB, RTLIB::SCMP, SignedFlagsArg, FlagsArg);
MIB.buildCopy(Register(Z80::F), SignedFlagsReg);
if (!RBI.constrainGenericRegister(FlagsReg, Z80::F8RegClass, MRI) ||
!RBI.constrainGenericRegister(SignedFlagsReg, Z80::F8RegClass, MRI))
if (!RBI.constrainGenericRegister(FlagsReg, Z80::Z8RegClass, MRI) ||
!RBI.constrainGenericRegister(SignedFlagsReg, Z80::Z8RegClass, MRI))
return Z80::COND_INVALID;
}
return CC;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp
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Expand Up @@ -46,7 +46,7 @@ Z80RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
if (Z80::R8RegClass.hasSubClassEq(&RC) ||
Z80::R16RegClass.hasSubClassEq(&RC) ||
Z80::R24RegClass.hasSubClassEq(&RC) ||
Z80::F8RegClass.hasSubClassEq(&RC) ||
Z80::Z8RegClass.hasSubClassEq(&RC) ||
Z80::Z16RegClass.hasSubClassEq(&RC) ||
Z80::Z24RegClass.hasSubClassEq(&RC))
return getRegBank(Z80::GPRRegBankID);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/Z80/Z80ISelLowering.cpp
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Expand Up @@ -632,15 +632,15 @@ Z80TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
}

if (Z80::parseConstraintCode(Constraint) != Z80::COND_INVALID)
return std::make_pair(Z80::F, &Z80::F8RegClass);
return std::make_pair(Z80::F, &Z80::Z8RegClass);

// Use the default implementation in TargetLowering to convert the register
// constraint into a member of a register class.
auto Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);

if (!Res.second) {
if (Constraint.equals_insensitive("{f}"))
return std::make_pair(Z80::F, &Z80::F8RegClass);
return std::make_pair(Z80::F, &Z80::Z8RegClass);

return Res;
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp
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Expand Up @@ -154,7 +154,7 @@ bool Z80MachineEarlyOptimization::runOnMachineFunction(MachineFunction &MF) {
}
}
if (CallMI && Cost < CondCallThreshold) {
Register TempReg = MRI.createVirtualRegister(&Z80::F8RegClass);
Register TempReg = MRI.createVirtualRegister(&Z80::Z8RegClass);
DebugLoc DL = MBB.findBranchDebugLoc();
MBB.removeSuccessor(FalseMBB);
TII.removeBranch(MBB);
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/Z80/Z80RegisterBanks.td
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Expand Up @@ -10,4 +10,4 @@
//===----------------------------------------------------------------------===//

/// General Purpose Registers
def GPRRegBank : RegisterBank<"GPR", [R24, Z24, Z16, F8]>;
def GPRRegBank : RegisterBank<"GPR", [R24, Z24, Z16, Z8]>;
11 changes: 8 additions & 3 deletions llvm/lib/Target/Z80/Z80RegisterInfo.td
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Expand Up @@ -101,7 +101,12 @@ let CostPerUse = [1] in {
def SPL : Z80Reg<"sp", 3>, DwarfRegNum<[7]>;

// misc registers
def PC : Z80Reg<"pc">, DwarfRegNum<[8]>;
def PC : Z80Reg<"pc">, DwarfRegNum<[8]>;
def I : Z80Reg<"i">;
let SubRegs = [I], SubRegIndices = [sub_low] in
def UI : Z80Reg<"i">;
def R : Z80Reg<"r">;
def MB : Z80Reg<"mb">;

//===----------------------------------------------------------------------===//
// Register Class Definitions...
Expand All @@ -118,7 +123,7 @@ def X8 : Z80RC8 <(add O8, IXL, IXH)>;
def I8 : Z80RC8 <(add IYL, IYH, IXL, IXH)>;
def R8 : Z80RC8 <(add G8, I8)>;
let CopyCost = -1 in
def F8 : Z80RC8 <(add F)>;
def Z8 : Z80RC8 <(add F, I, R, MB)>;

def O16 : Z80RC16<(add DE, BC)>;
def G16 : Z80RC16<(add HL, O16)>;
Expand All @@ -128,7 +133,7 @@ def I16 : Z80RC16<(add IY, IX)>;
def A16 : Z80RC16<(add HL, I16)>;
def R16 : Z80RC16<(add G16, I16)>;
let CopyCost = -1 in
def Z16 : Z80RC16<(add SPS, AF)>;
def Z16 : Z80RC16<(add SPS, AF, UI)>;

def O24 : Z80RC24<(add UDE, UBC)>;
def G24 : Z80RC24<(add UHL, O24)>;
Expand Down