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[SYCL][Matrix spec] Add 1x64x16 combination for Intel XMX (PVC only) #13587

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Merged
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Apr 30, 2024
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[SYCL][Matrix spec] Add 1x64x16 combination for Intel XMX (PVC only) #13587

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12 changes: 7 additions & 5 deletions sycl/doc/extensions/experimental/sycl_ext_matrix/sycl_ext_oneapi_matrix.asciidoc
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@
== Notice

[%hardbreaks]
Copyright (c) 2021-2023 Intel Corporation. All rights reserved.
Copyright (c) 2021-2024 Intel Corporation. All rights reserved.

Khronos(R) is a registered trademark and SYCL(TM) and SPIR(TM) are trademarks
of The Khronos Group Inc. OpenCL(TM) is a trademark of Apple Inc. used by
Expand Down Expand Up @@ -1011,9 +1011,9 @@ architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
`architecture::intel_gpu_pvc`
|8| `architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
.4+| `matrix_type::bf16` .4+| `matrix_type::bf16` .4+|
`matrix_type::fp32` | 16 | 16 | 16 .3+|`architecture::intel_gpu_pvc`
|32 | 64 | 16
.5+| `matrix_type::bf16` .5+| `matrix_type::bf16` .5+|
`matrix_type::fp32` | 16 | 16 | 16 .4+|`architecture::intel_gpu_pvc`
| 1 | 64 | 16 | 32 | 64 | 16
.2+| +<=+ 8 | 16 .2+| 16
|8 | `architecture::intel_gpu_dg2_g10,
architecture::intel_gpu_dg2_g11, architecture::intel_gpu_dg2_g12`
Expand Down Expand Up @@ -1131,6 +1131,8 @@ and Intel XMX
|8 |2023-10-05 |Mahmoud Moadeli |Add AMD Matrix Core supported combinations
|9 |2023-11-13 |Dounia Khaldi |Add Granite Rapids Intel AMX
supported combinations
|9 |2023-12-04 |Dounia Khaldi |Add prefetch and `annotated_ptr`
|10 |2023-12-04 |Dounia Khaldi |Add prefetch and `annotated_ptr`
load/store overloads
|11 |2024-04-29 |Yury Plyakhin | Add 1x64x16 supported combination for
Intel XMX (intel_gpu_pvc)
|======================