[AArch64InstPrinter] Change printAlignedLabel to print the target address in hexadecimal form

Similar to D76580 (x86) and D76591 (PPC).

```
// llvm-objdump -d output (before)
10000: 08 00 00 94                   bl      #32
10004: 08 00 00 94                   bl      #32

// llvm-objdump -d output (after)
10000: 08 00 00 94                   bl      0x10020
10004: 08 00 00 94                   bl      0x10024

// GNU objdump -d. The lack of 0x is not ideal due to ambiguity.
10000:       94000008        bl      10020 <bar+0x18>
10004:       94000008        bl      10024 <bar+0x1c>
```

The new output makes it easier to find the jump target.

Differential Revision: https://reviews.llvm.org/D77853

Author: MaskRay

lld/test/COFF/arm64-delayimport.yaml

@@ -7,7 +7,7 @@
 
 # DISASM:  140001014:      11 00 00 d0     adrp    x17, #8192
 # DISASM:  140001018:      31 22 00 91     add     x17, x17, #8
-# DISASM:  14000101c:      01 00 00 14     b       #4 <.text+0x20>
+# DISASM:  14000101c:      01 00 00 14     b       0x140001020 <.text+0x20>
 # DISASM:  140001020:      fd 7b b3 a9     stp     x29, x30, [sp, #-208]!
 # DISASM:  140001024:      fd 03 00 91     mov     x29, sp
 # DISASM:  140001028:      e0 07 01 a9     stp     x0, x1, [sp, #16]
@@ -21,7 +21,7 @@
 # DISASM:  140001048:      e1 03 11 aa     mov     x1, x17
 # DISASM:  14000104c:      00 00 00 b0     adrp    x0, #4096
 # DISASM:  140001050:      00 00 00 91     add     x0, x0, #0
-# DISASM:  140001054:      eb ff ff 97     bl      #-84 <.text>
+# DISASM:  140001054:      eb ff ff 97     bl      0x140001000 <.text>
 # DISASM:  140001058:      f0 03 00 aa     mov     x16, x0
 # DISASM:  14000105c:      e6 9f 45 ad     ldp     q6, q7, [sp, #176]
 # DISASM:  140001060:      e4 97 44 ad     ldp     q4, q5, [sp, #144]

lld/test/COFF/arm64-import2.test

@@ -8,14 +8,14 @@
 
 # BEFORE: Disassembly of section .text:
 # BEFORE-EMPTY:
-# BEFORE:        0:       00 00 00 94     bl      #0
-# BEFORE:        4:       00 00 00 94     bl      #0
+# BEFORE:        0:       00 00 00 94     bl      0x0
+# BEFORE:        4:       00 00 00 94     bl      0x4
 # BEFORE:        8:       c0 03 5f d6     ret
 
 # AFTER: Disassembly of section .text:
 # AFTER-EMPTY:
-# AFTER:  140001000:      03 00 00 94     bl      #12
-# AFTER:  140001004:      05 00 00 94     bl      #20
+# AFTER:  140001000:      03 00 00 94     bl      0x14000100c
+# AFTER:  140001004:      05 00 00 94     bl      0x140001018
 # AFTER:  140001008:      c0 03 5f d6     ret
 # AFTER:  14000100c:      10 00 00 b0     adrp    x16, #4096
 # AFTER:  140001010:      10 32 40 f9     ldr     x16, [x16, #96]

lld/test/COFF/arm64-relocs-imports.test

@@ -10,7 +10,7 @@
 # BEFORE:        0:       fe 0f 1f f8     str     x30, [sp, #-16]!
 # BEFORE:        4:       00 00 00 90     adrp    x0, #0
 # BEFORE:        8:       00 08 00 91     add     x0, x0, #2
-# BEFORE:        c:       00 00 00 94     bl      #0
+# BEFORE:        c:       00 00 00 94     bl      0xc
 # BEFORE:       10:       00 01 40 39     ldrb    w0, [x8]
 # BEFORE:       14:       00 01 40 79     ldrh    w0, [x8]
 # BEFORE:       18:       00 01 40 b9     ldr     w0, [x8]
@@ -44,16 +44,16 @@
 # BEFORE:       88:       00 00 40 f9     ldr     x0, [x0]
 # BEFORE:       8c:       01 00 00 00     udf #1
 # BEFORE:       90:       20 1a 09 30     adr x0, #74565
-# BEFORE:       94:       01 00 00 54     b.ne    #0
-# BEFORE:       98:       00 00 00 36     tbz     w0, #0, #0
+# BEFORE:       94:       01 00 00 54     b.ne    0x94
+# BEFORE:       98:       00 00 00 36     tbz     w0, #0, 0x98
 # BEFORE:       9c:       01 00 00 00     udf #1
 
 # AFTER: Disassembly of section .text:
 # AFTER-EMPTY:
 # AFTER:  140001000:      fe 0f 1f f8     str     x30, [sp, #-16]!
 # AFTER:  140001004:      00 00 00 b0     adrp    x0, #4096
 # AFTER:  140001008:      00 18 00 91     add     x0, x0, #6
-# AFTER:  14000100c:      25 00 00 94     bl      #148
+# AFTER:  14000100c:      25 00 00 94     bl      0x1400010a0
 # AFTER:  140001010:      00 21 40 39     ldrb    w0, [x8, #8]
 # AFTER:  140001014:      00 11 40 79     ldrh    w0, [x8, #8]
 # AFTER:  140001018:      00 09 40 b9     ldr     w0, [x8, #8]
@@ -87,8 +87,8 @@
 # AFTER:  140001088:      00 c4 41 f9     ldr     x0, [x0, #904]
 # AFTER:  14000108c:      03 00 00 00     udf #3
 # AFTER:  140001090:      e0 95 09 30     adr     x0, #78525
-# AFTER:  140001094:      61 00 00 54     b.ne    #12
-# AFTER:  140001098:      40 00 00 36     tbz     w0, #0, #8
+# AFTER:  140001094:      61 00 00 54     b.ne    0x1400010a0
+# AFTER:  140001098:      40 00 00 36     tbz     w0, #0, 0x1400010a0
 # AFTER:  14000109c:      61 ff ff ff     <unknown>
 # AFTER:  1400010a0:      10 00 00 b0     adrp    x16, #4096
 # AFTER:  1400010a4:      10 2a 40 f9     ldr     x16, [x16, #80]

lld/test/COFF/arm64-thunks.s

@@ -27,13 +27,13 @@ func2:
     ret
 
 // DISASM: 0000000140001000 <.text>:
-// DISASM: 140001000:      40 00 00 36     tbz     w0, #0, #8 <.text+0x8>
+// DISASM: 140001000:      40 00 00 36     tbz     w0, #0, 0x140001008 <.text+0x8>
 // DISASM: 140001004:      c0 03 5f d6     ret
 // DISASM: 140001008:      50 00 00 90     adrp    x16, #32768
 // DISASM: 14000100c:      10 52 00 91     add     x16, x16, #20
 // DISASM: 140001010:      00 02 1f d6     br      x16
 
-// DISASM: 140009014:      60 00 00 36     tbz     w0, #0, #12 <.text+0x8020>
+// DISASM: 140009014:      60 00 00 36     tbz     w0, #0, 0x140009020 <.text+0x8020>
 // DISASM: 140009018:      c0 03 5f d6     ret
 
 // DISASM: 140009020:      50 00 00 90     adrp    x16, #32768

lld/test/ELF/aarch64-call26-thunk.s

@@ -12,9 +12,9 @@ _start:
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    210120:       bl      #4
+// CHECK-NEXT:    210120:       bl      0x210124
 // CHECK: <__AArch64AbsLongThunk_big>:
-// CHECK-NEXT:    210124:       ldr     x16, #8
+// CHECK-NEXT:    210124:       ldr     x16, 0x21012c
 // CHECK-NEXT:    210128:       br      x16
 // CHECK: <$d>:
 // CHECK-NEXT:    21012c:       00 00 00 00     .word   0x00000000

lld/test/ELF/aarch64-condb-reloc.s

@@ -25,9 +25,9 @@
 # CHECK-NEXT:    21013c: nop
 # CHECK-NEXT:    210140: nop
 # CHECK:      <_start>:
-# CHECK-NEXT:    210144: b.eq #-36 <_foo>
-# CHECK-NEXT:    210148: b.eq #-24 <_bar>
-# CHECK-NEXT:    21014c: b.eq #-16 <_dah>
+# CHECK-NEXT:    210144: b.eq 0x210120 <_foo>
+# CHECK-NEXT:    210148: b.eq 0x210130 <_bar>
+# CHECK-NEXT:    21014c: b.eq 0x21013c <_dah>
 
 #DSOREL:      Section {
 #DSOREL:        Index:
@@ -68,9 +68,9 @@
 #DSO-NEXT:     10354: nop
 #DSO-NEXT:     10358: nop
 #DSO:      <_start>:
-#DSO-NEXT:     1035c: b.eq #52 <_foo@plt>
-#DSO-NEXT:     10360: b.eq #64 <_bar@plt>
-#DSO-NEXT:     10364: b.eq #76 <_dah@plt>
+#DSO-NEXT:     1035c: b.eq 0x10390 <_foo@plt>
+#DSO-NEXT:     10360: b.eq 0x103a0 <_bar@plt>
+#DSO-NEXT:     10364: b.eq 0x103b0 <_dah@plt>
 #DSO-EMPTY:
 #DSO-NEXT: Disassembly of section .plt:
 #DSO-EMPTY:

lld/test/ELF/aarch64-cortex-a53-843419-address.s

@@ -40,7 +40,7 @@
 // CHECK: <t3_ff8_ldr>:
 // CHECK-NEXT:      ff8:        20 00 00 d0     adrp    x0, #24576
 // CHECK-NEXT:      ffc:        21 00 40 f9     ldr             x1, [x1]
-// CHECK-NEXT:     1000:        f9 0f 00 14     b       #16356
+// CHECK-NEXT:     1000:        f9 0f 00 14     b       0x4fe4
 // CHECK-NEXT:     1004:        c0 03 5f d6     ret
         .section .text.01, "ax", %progbits
         .balign 4096
@@ -62,7 +62,7 @@ $x.999:
 // CHECK: <t3_ffc_ldrsimd>:
 // CHECK-NEXT:     1ffc:        20 00 00 b0     adrp    x0, #20480
 // CHECK-NEXT:     2000:        21 00 40 bd     ldr             s1, [x1]
-// CHECK-NEXT:     2004:        fa 0b 00 14     b       #12264
+// CHECK-NEXT:     2004:        fa 0b 00 14     b       0x4fec
 // CHECK-NEXT:     2008:        c0 03 5f d6     ret
         .globl t3_ffc_ldrsimd
         .type t3_ffc_ldrsimd, %function
@@ -99,7 +99,7 @@ t3_ff8_ldralldata:
 // CHECK: <t3_ffc_ldr>:
 // CHECK-NEXT:     3ff8:        00 00 00 f0     adrp    x0, #12288
 // CHECK-NEXT:     3ffc:        21 00 40 f9     ldr             x1, [x1]
-// CHECK-NEXT:     4000:        fd 03 00 14     b       #4084
+// CHECK-NEXT:     4000:        fd 03 00 14     b       0x4ff4
 // CHECK-NEXT:     4004:        c0 03 5f d6     ret
         .space 4096 - 12
         .globl t3_ffc_ldr
@@ -112,13 +112,13 @@ t3_ff8_ldralldata:
 
 // CHECK: <__CortexA53843419_1000>:
 // CHECK-NEXT:     4fe4:        00 0c 40 f9     ldr     x0, [x0, #24]
-// CHECK-NEXT:     4fe8:        07 f0 ff 17     b       #-16356
+// CHECK-NEXT:     4fe8:        07 f0 ff 17     b       0x1004
 // CHECK: <__CortexA53843419_2004>:
 // CHECK-NEXT:     4fec:        02 0c 40 f9     ldr     x2, [x0, #24]
-// CHECK-NEXT:     4ff0:        06 f4 ff 17     b       #-12264
+// CHECK-NEXT:     4ff0:        06 f4 ff 17     b       0x2008
 // CHECK: <__CortexA53843419_4000>:
 // CHECK-NEXT:     4ff4:        00 0c 40 f9     ldr     x0, [x0, #24]
-// CHECK-NEXT:     4ff8:        03 fc ff 17     b       #-4084
+// CHECK-NEXT:     4ff8:        03 fc ff 17     b       0x4004
 
         .section .text.02, "ax", %progbits
         .space 4096 - 36
@@ -131,7 +131,7 @@ t3_ff8_ldralldata:
 // CHECK: <t3_ffc_str>:
 // CHECK-NEXT:     4ffc:        00 00 00 d0     adrp    x0, #8192
 // CHECK-NEXT:     5000:        21 00 00 f9     str             x1, [x1]
-// CHECK-NEXT:     5004:        fb 03 00 14     b       #4076
+// CHECK-NEXT:     5004:        fb 03 00 14     b       0x5ff0
 // CHECK-NEXT:     5008:        c0 03 5f d6     ret
 
         .section .newisd, "ax", %progbits
@@ -146,7 +146,7 @@ t3_ffc_str:
 
 // CHECK: <__CortexA53843419_5004>:
 // CHECK-NEXT:     5ff0:        00 0c 40 f9     ldr     x0, [x0, #24]
-// CHECK-NEXT:     5ff4:        05 fc ff 17     b       #-4076
+// CHECK-NEXT:     5ff4:        05 fc ff 17     b       0x5008
 
         // Start a new OutputSection (see Linker Script) so the
         // start address will be affected by any patches added to previous
@@ -156,7 +156,7 @@ t3_ffc_str:
 // CHECK: <t3_ff8_str>:
 // CHECK-NEXT:     5ff8:        00 00 00 b0     adrp    x0, #4096
 // CHECK-NEXT:     5ffc:        21 00 00 f9     str             x1, [x1]
-// CHECK-NEXT:     6000:        03 00 00 14     b       #12
+// CHECK-NEXT:     6000:        03 00 00 14     b       0x600c
 // CHECK-NEXT:     6004:        c0 03 5f d6     ret
 
         .section .newos, "ax", %progbits
@@ -174,7 +174,7 @@ _start:
 
 // CHECK: <__CortexA53843419_6000>:
 // CHECK-NEXT:     600c:        00 0c 40 f9     ldr     x0, [x0, #24]
-// CHECK-NEXT:     6010:        fd ff ff 17     b       #-12
+// CHECK-NEXT:     6010:        fd ff ff 17     b       0x6004
 
         .data
         .globl dat

lld/test/ELF/aarch64-cortex-a53-843419-large.s

@@ -13,7 +13,7 @@
 // required.					      
 
 // CHECK1:  <__AArch64AbsLongThunk_need_thunk_after_patch>:
-// CHECK1-NEXT:    210000:       50 00 00 58     ldr     x16, #8
+// CHECK1-NEXT:    210000:       50 00 00 58     ldr     x16, 0x210008
 // CHECK1-NEXT:    210004:       00 02 1f d6     br      x16
 // CHECK1: <$d>:
 // CHECK1-NEXT:    210008:       0c 10 21 08     .word   0x0821100c
@@ -29,7 +29,7 @@ _start:
         .space 4096 - 12
 
 // CHECK2: <_start>:
-// CHECK2-NEXT:    211000:       00 fc ff 97     bl      #-4096
+// CHECK2-NEXT:    211000:       00 fc ff 97     bl      0x210000
 
         // Expect patch on pass 1
         .section .text.03, "ax", %progbits
@@ -44,7 +44,7 @@ t3_ff8_ldr:
 // CHECK3: <t3_ff8_ldr>:
 // CHECK3-NEXT:    211ff8:       e0 00 04 f0     adrp    x0, #134344704
 // CHECK3-NEXT:    211ffc:       21 00 40 f9     ldr     x1, [x1]
-// CHECK3-NEXT:    212000:       02 08 80 15     b       #100671496
+// CHECK3-NEXT:    212000:       02 08 80 15     b       0x6214008
 // CHECK3-NEXT:    212004:       c0 03 5f d6     ret
 
         .section .text.04, "ax", %progbits
@@ -65,18 +65,18 @@ t3_ff8_str:
 // CHECK4: <t3_ff8_str>:
 // CHECK4-NEXT:  4213ff8:       e0 00 02 b0     adrp    x0, #67227648
 // CHECK4-NEXT:  4213ffc:       21 00 40 f9     ldr     x1, [x1]
-// CHECK4-NEXT:  4214000:       04 00 80 14     b       #33554448
+// CHECK4-NEXT:  4214000:       04 00 80 14     b       0x6214010
 // CHECK4-NEXT:  4214004:       c0 03 5f d6     ret
 
         .section .text.06, "ax", %progbits
         .space 32 * 1024 * 1024
 
 // CHECK5: <__CortexA53843419_211000>:
 // CHECK5-NEXT:  6214008:       00 00 40 f9     ldr     x0, [x0]
-// CHECK5-NEXT:  621400c:       fe f7 7f 16     b       #-100671496
+// CHECK5-NEXT:  621400c:       fe f7 7f 16     b       0x212004
 // CHECK5: <__CortexA53843419_4213000>:
 // CHECK5-NEXT:  6214010:       00 00 00 f9     str     x0, [x0]
-// CHECK5-NEXT:  6214014:       fc ff 7f 17     b       #-33554448
+// CHECK5-NEXT:  6214014:       fc ff 7f 17     b       0x4214004
 
         .section .text.07, "ax", %progbits
         .space (32 * 1024 * 1024) - 12300
@@ -104,11 +104,11 @@ t3_ffc_ldr:
 // CHECK7: <t3_ffc_ldr>:
 // CHECK7-NEXT:  8211ffc:       e0 00 00 f0     adrp    x0, #126976
 // CHECK7-NEXT:  8212000:       21 00 40 f9     ldr     x1, [x1]
-// CHECK7-NEXT:  8212004:       02 00 00 14     b       #8
+// CHECK7-NEXT:  8212004:       02 00 00 14     b       0x821200c
 // CHECK7-NEXT:  8212008:       c0 03 5f d6     ret
 // CHECK7: <__CortexA53843419_8212004>:
 // CHECK7-NEXT:  821200c:       00 00 40 f9     ldr     x0, [x0]
-// CHECK7-NEXT:  8212010:       fe ff ff 17     b       #-8
+// CHECK7-NEXT:  8212010:       fe ff ff 17     b       0x8212008
 
         .section .data
         .globl dat

lld/test/ELF/aarch64-cortex-a53-843419-large2.s

@@ -9,7 +9,7 @@
 adrp x0, thunk
 ldr x1, [x1, #0]
 // CHECK: <thunk>:
-// CHECK-NEXT: b #67108872 <__CortexA53843419_8001000>
+// CHECK-NEXT: b 0xc001008 <__CortexA53843419_8001000>
 thunk:
 ldr x0, [x0, :got_lo12:thunk]
 ret