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rez5427Yui5427arsenmRKSimon
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[DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) (#155141)
Hi, I compared the following LLVM IR with GCC and Clang, and there is a small difference between the two. The LLVM IR is: ``` define i64 @test_smin_neg_one(i64 %a) { %1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1) %retval.0 = xor i64 %1, -1 ret i64 %retval.0 } ``` GCC generates: ``` cmp x0, 0 csinv x0, xzr, x0, ge ret ``` Clang generates: ``` cmn x0, #1 csinv x8, x0, xzr, lt mvn x0, x8 ret ``` Clang keeps flipping x0 through x8 unnecessarily. So I added the following folds to DAGCombiner: fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0 fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0 alive2: https://alive2.llvm.org/ce/z/gffoir --------- Co-authored-by: Yui5427 <[email protected]> Co-authored-by: Matt Arsenault <[email protected]> Co-authored-by: Simon Pilgrim <[email protected]>
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10092,6 +10092,55 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
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return Combined;
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// fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0
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// fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
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// fold (xor (umin(x, C), C)) -> select (x < C), xor(x, C), 0
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// fold (xor (umax(x, C), C)) -> select (x > C), xor(x, C), 0
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SDValue Op0;
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if (sd_match(N0, m_OneUse(m_AnyOf(m_SMin(m_Value(Op0), m_Specific(N1)),
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m_SMax(m_Value(Op0), m_Specific(N1)),
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m_UMin(m_Value(Op0), m_Specific(N1)),
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m_UMax(m_Value(Op0), m_Specific(N1)))))) {
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10105+
if (isa<ConstantSDNode>(N1) ||
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ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
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// For vectors, only optimize when the constant is zero or all-ones to
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// avoid generating more instructions
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if (VT.isVector()) {
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ConstantSDNode *N1C = isConstOrConstSplat(N1);
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if (!N1C || (!N1C->isZero() && !N1C->isAllOnes()))
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return SDValue();
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}
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// Avoid the fold if the minmax operation is legal and select is expensive
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if (TLI.isOperationLegal(N0.getOpcode(), VT) &&
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TLI.isPredictableSelectExpensive())
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return SDValue();
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EVT CCVT = getSetCCResultType(VT);
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ISD::CondCode CC;
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switch (N0.getOpcode()) {
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case ISD::SMIN:
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CC = ISD::SETLT;
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break;
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case ISD::SMAX:
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CC = ISD::SETGT;
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break;
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case ISD::UMIN:
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CC = ISD::SETULT;
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break;
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case ISD::UMAX:
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CC = ISD::SETUGT;
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break;
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}
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SDValue FN1 = DAG.getFreeze(N1);
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SDValue Cmp = DAG.getSetCC(DL, CCVT, Op0, FN1, CC);
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SDValue XorXC = DAG.getNode(ISD::XOR, DL, VT, Op0, FN1);
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SDValue Zero = DAG.getConstant(0, DL, VT);
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return DAG.getSelect(DL, VT, Cmp, XorXC, Zero);
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}
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}
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return SDValue();
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}
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‎llvm/test/CodeGen/AArch64/xor-min-max.ll‎

Lines changed: 196 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,196 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s
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; Test for DAGCombiner optimization: fold (xor (smin(x, C), C)) -> select (x < C), xor (x, C), 0
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define i64 @test_smin_neg_one(i64 %a) {
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; CHECK-LABEL: test_smin_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmn x0, #1
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; CHECK-NEXT: csinv x0, xzr, x0, ge
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_smin_constant(i64 %a) {
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; CHECK-LABEL: test_smin_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, lt
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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; Test for DAGCombiner optimization: fold (xor (smax(x, C), C)) -> select (x > C), xor (x, C), 0
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define i64 @test_smax_neg_one(i64 %a) {
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; CHECK-LABEL: test_smax_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x0
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; CHECK-NEXT: bic x0, x8, x0, asr #63
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_smax_constant(i64 %a) {
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; CHECK-LABEL: test_smax_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, gt
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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define i64 @test_umin_neg_one(i64 %a) {
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; CHECK-LABEL: test_umin_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x0, x0
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_umin_constant(i64 %a) {
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; CHECK-LABEL: test_umin_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, lo
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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define i64 @test_umax_neg_one(i64 %a) {
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; CHECK-LABEL: test_umax_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 -1)
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%retval.0 = xor i64 %1, -1
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ret i64 %retval.0
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}
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define i64 @test_umax_constant(i64 %a) {
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; CHECK-LABEL: test_umax_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: eor x8, x0, #0x8
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; CHECK-NEXT: cmp x0, #8
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; CHECK-NEXT: csel x0, x8, xzr, hi
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 8)
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%retval.0 = xor i64 %1, 8
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ret i64 %retval.0
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}
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; Test vector cases
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define <4 x i32> @test_smin_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_smin_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
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; CHECK-NEXT: cmgt v1.4s, v1.4s, v0.4s
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
107+
ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smin_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_smin_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smax_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_smax_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmge v1.4s, v0.4s, #0
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_smax_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_smax_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
143+
}
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define <4 x i32> @test_umin_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_umin_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
153+
}
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define <4 x i32> @test_umin_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_umin_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umax_vector_neg_one(<4 x i32> %a) {
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; CHECK-LABEL: test_umax_vector_neg_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
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%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %retval.0
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}
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define <4 x i32> @test_umax_vector_constant(<4 x i32> %a) {
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; CHECK-LABEL: test_umax_vector_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.4s, #8
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; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 8, i32 8, i32 8, i32 8>)
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%retval.0 = xor <4 x i32> %1, <i32 8, i32 8, i32 8, i32 8>
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ret <4 x i32> %retval.0
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}
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declare i64 @llvm.smin.i64(i64, i64)
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declare i64 @llvm.smax.i64(i64, i64)
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declare i64 @llvm.umin.i64(i64, i64)
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declare i64 @llvm.umax.i64(i64, i64)
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declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)

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