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| 1 | +;=========================== begin_copyright_notice ============================ |
| 2 | +; |
| 3 | +; Copyright (C) 2025 Intel Corporation |
| 4 | +; |
| 5 | +; SPDX-License-Identifier: MIT |
| 6 | +; |
| 7 | +;============================ end_copyright_notice ============================= |
| 8 | + |
| 9 | +; REQUIRES: regkeys |
| 10 | +; RUN: igc_opt --opaque-pointers --regkey DisableCodeScheduling=0 --regkey EnableCodeSchedulingIfNoSpills=1 \ |
| 11 | +; RUN: --regkey PrintToConsole=1 --regkey DumpCodeScheduling=1 --igc-code-scheduling \ |
| 12 | +; RUN: --regkey CodeSchedulingRPThreshold=-512 \ |
| 13 | +; RUN: --regkey ForceOCLSIMDWidth=16 -S %s 2>&1 | FileCheck %s |
| 14 | + |
| 15 | + |
| 16 | +; Checks that the register pressure is estimated correctly for the special cases related to |
| 17 | +; addrspace cast and pointer/int casts |
| 18 | + |
| 19 | +define void @test_lsc2dblockread(i64 %base_addr, i64 %offset, i32 %shift_val) { |
| 20 | +; CHECK: Function test_lsc2dblockread |
| 21 | +; CHECK: Original schedule: entry |
| 22 | + |
| 23 | +entry: |
| 24 | +; Calculate address components |
| 25 | +; The first instruction adds a new value (the argument doesn't die) |
| 26 | + |
| 27 | +; CHECK: {{\([0-9]+,[ ]*64[ ]*\) OG:[ A-Z]*}} [[ADDR_SHIFT:%.*]] = shl i32 [[SHIFT_VAL:%.*]], 6 |
| 28 | + %addr_shift = shl i32 %shift_val, 6 |
| 29 | + |
| 30 | +; The second instruction should also estimate the register pressure increase |
| 31 | +; Because we extend to a larger data type |
| 32 | + |
| 33 | +; CHECK: {{\([0-9]+,[ ]*64[ ]*\) OG:[ A-Z]*}} [[ADDR_SHIFT_EXT:%.*]] = zext i32 [[ADDR_SHIFT]] to i64 |
| 34 | + %addr_shift_ext = zext i32 %addr_shift to i64 |
| 35 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[BASE_PLUS_SHIFT:%.*]] = add i64 [[BASE_ADDR:%.*]], [[ADDR_SHIFT_EXT]] |
| 36 | + %base_plus_shift = add i64 %base_addr, %addr_shift_ext |
| 37 | + |
| 38 | +; No changes as we continue calculating the address and perform various casts |
| 39 | + |
| 40 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[FINAL_ADDR:%.*]] = add i64 [[BASE_PLUS_SHIFT]], [[OFFSET:%.*]] |
| 41 | + %final_addr = add i64 %base_plus_shift, %offset |
| 42 | + |
| 43 | +; Convert to pointer and back through address spaces |
| 44 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[PTR_AS1:%.*]] = inttoptr i64 [[FINAL_ADDR]] to ptr addrspace(1) |
| 45 | + %ptr_as1 = inttoptr i64 %final_addr to i8 addrspace(1)* |
| 46 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[PTR_AS4:%.*]] = addrspacecast ptr addrspace(1) [[PTR_AS1]] to ptr addrspace(4) |
| 47 | + %ptr_as4 = addrspacecast i8 addrspace(1)* %ptr_as1 to i8 addrspace(4)* |
| 48 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[ADDR_AS4:%.*]] = ptrtoint ptr addrspace(4) [[PTR_AS4]] to i64 |
| 49 | + %addr_as4 = ptrtoint i8 addrspace(4)* %ptr_as4 to i64 |
| 50 | + |
| 51 | +; Convert to pointer pair |
| 52 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[PTR_PAIR:%.*]] = call { i32, i32 } @llvm.genx.GenISA.ptr.to.pair.p4i8(ptr addrspace(4) [[PTR_AS4]]) |
| 53 | + %ptr_pair = call { i32, i32 } @llvm.genx.GenISA.ptr.to.pair.p4i8(i8 addrspace(4)* %ptr_as4) |
| 54 | + |
| 55 | +; Currently it's estimated as +64 -64: essentially correct, but |
| 56 | +; may be not perfect for the instruction choosing heuristics |
| 57 | +; CHECK: {{\([0-9]+,[ ]*64[ ]*\) OG:[ A-Z]*}} [[PAIR_LOW:%.*]] = extractvalue { i32, i32 } [[PTR_PAIR]], 0 |
| 58 | + %pair_low = extractvalue { i32, i32 } %ptr_pair, 0 |
| 59 | +; CHECK: {{\([0-9]+,[ ]*-64[ ]*\) OG:[ A-Z]*}} [[PAIR_HIGH:%.*]] = extractvalue { i32, i32 } [[PTR_PAIR]], 1 |
| 60 | + %pair_high = extractvalue { i32, i32 } %ptr_pair, 1 |
| 61 | + |
| 62 | +; Prepare the first parameter (base address as i64) |
| 63 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[ALIGNED_LOW:%.*]] = and i32 [[PAIR_LOW]], -64 |
| 64 | + %aligned_low = and i32 %pair_low, -64 |
| 65 | + |
| 66 | +; Estimated as +128 -128 |
| 67 | +; CHECK: {{\([0-9]+,[ ]*128[ ]*\) OG:[ A-Z]*}} [[VEC_LOW:%.*]] = insertelement <2 x i32> undef, i32 [[ALIGNED_LOW]], i32 0 |
| 68 | + %vec_low = insertelement <2 x i32> undef, i32 %aligned_low, i32 0 |
| 69 | +; CHECK: {{\([0-9]+,[ ]*-128[ ]*\) OG:[ A-Z]*}} [[VEC_PAIR:%.*]] = insertelement <2 x i32> [[VEC_LOW]], i32 [[PAIR_HIGH]], i32 1 |
| 70 | + %vec_pair = insertelement <2 x i32> %vec_low, i32 %pair_high, i32 1 |
| 71 | + |
| 72 | +; Bitcast is a no-op |
| 73 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[BASE_ADDR_PARAM:%.*]] = bitcast <2 x i32> [[VEC_PAIR]] to i64 |
| 74 | + %base_addr_param = bitcast <2 x i32> %vec_pair to i64 |
| 75 | + |
| 76 | +; Prepare the coordinate parameter |
| 77 | +; Truncation decreases the register pressure as the return type becomes smaller |
| 78 | +; CHECK: {{\([0-9]+,[ ]*-64[ ]*\) OG:[ A-Z]*}} [[ADDR_TRUNC:%.*]] = trunc i64 [[ADDR_AS4]] to i32 |
| 79 | + %addr_trunc = trunc i64 %addr_as4 to i32 |
| 80 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[COORD_SHIFT:%.*]] = lshr i32 [[ADDR_TRUNC]], 1 |
| 81 | + %coord_shift = lshr i32 %addr_trunc, 1 |
| 82 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} [[COORD_MASKED:%.*]] = and i32 [[COORD_SHIFT]], 31 |
| 83 | + %coord_masked = and i32 %coord_shift, 31 |
| 84 | + |
| 85 | +; Execute the LSC2DBlockRead: 256 (i16 * v8 * SIMD16) - 128 (i64 x SIMD16) - 64 (i32 * SIMD16) |
| 86 | +; CHECK: {{\([0-9]+,[ ]*64[ ]*\) OG:[ A-Z]*}} [[LOAD_RESULT:%.*]] = call <8 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v8i16(i64 [[BASE_ADDR_PARAM]], i32 4095, i32 7, i32 4095, i32 [[COORD_MASKED]], i32 0, i32 16, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0) |
| 87 | + %load_result = call <8 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v8i16(i64 %base_addr_param, i32 4095, i32 7, i32 4095, i32 %coord_masked, i32 0, i32 16, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0) |
| 88 | + |
| 89 | +; Execute the DPAS |
| 90 | +; Returns the 2x larger type as the load, load dies |
| 91 | +; CHECK: {{\([0-9]+,[ ]*256[ ]*\) OG:[ A-Z]*}} [[DPAS_RESULT:%.*]] = call <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float> zeroinitializer, <8 x i16> [[LOAD_RESULT]], <8 x i32> zeroinitializer, i32 1, i32 1, i32 1, i32 1, i1 false) |
| 92 | + %dpas_result = call <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float> zeroinitializer, <8 x i16> %load_result, <8 x i32> zeroinitializer, i32 1, i32 1, i32 1, i32 1, i1 false) |
| 93 | +; CHECK: {{\([0-9]+,[ ]*0[ ]*\) OG:[ A-Z]*}} ret void |
| 94 | + ret void |
| 95 | +} |
| 96 | + |
| 97 | + |
| 98 | +declare <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32( |
| 99 | + <8 x float>, <8 x i16>, <8 x i32>, i32, i32, i32, i32, i1) #1 |
| 100 | + |
| 101 | +declare <8 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v8i16(i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i1, i1, i32) #1 |
| 102 | +declare { i32, i32 } @llvm.genx.GenISA.ptr.to.pair.p4i8(i8 addrspace(4)*) #3 |
| 103 | + |
| 104 | +attributes #0 = { convergent nounwind } |
| 105 | +attributes #1 = { convergent nounwind readnone willreturn } |
| 106 | +attributes #2 = { nofree nosync nounwind readnone speculatable willreturn } |
| 107 | +attributes #3 = { nounwind readnone willreturn } |
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