Skip to content

Commit d7f6ac0

Browse files
committed
Updated meta data & documentation
1 parent 250522f commit d7f6ac0

File tree

7 files changed

+33
-6
lines changed

7 files changed

+33
-6
lines changed

io-classes-mtl/io-classes-mtl.cabal

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,10 @@ cabal-version: 3.0
22
name: io-classes-mtl
33
version: 0.1.0.0
44
synopsis: Experimental MTL instances for io-classes
5+
description:
6+
MTL instances for
7+
[io-classes](https://hackage.hasekll.org/package/io-classes) package.
8+
Some of the instances are novel and some are still experimental.
59
license: Apache-2.0
610
license-files:
711
LICENSE

io-classes/io-classes.cabal

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,10 @@ cabal-version: 3.0
22
name: io-classes
33
version: 1.0.0.0
44
synopsis: Type classes for concurrency with STM, ST and timing
5+
description:
6+
IO Monad class hierarchy compatible with
7+
[io-sim](https://hackage.haskell.org/package/io-sim), 'base', 'async',
8+
'stm', 'exceptions' & 'time' packages.
59
license: Apache-2.0
610
license-files:
711
LICENSE

io-sim/io-sim.cabal

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
11
cabal-version: 3.0
22
name: io-sim
33
version: 1.0.0.0
4-
synopsis: A pure simulator for monadic concurrency with STM
4+
synopsis: A pure simulator for monadic concurrency with STM.
5+
description:
6+
A pure simulator monad with support of concurency (base, async), stm,
7+
synchronous and asynchronous exceptions, timeouts & delays, dynamic traces,
8+
and more.
59
license: Apache-2.0
610
license-files:
711
LICENSE

si-timers/README.md

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@ very efficient but for other platforms (e.g. `Windows`), it might not be the
1313
right API for low latency timeouts needed for example for low level networking
1414
code, because it relies on `GHC`'s `RTS` thread scheduling.
1515

16+
`si-timers` are compatible with `io-sim`.
17+
1618
The `SI` comes from the [International System of Units][SI].
1719

1820
[SI]: https://www.wikiwand.com/en/International_System_of_Units
21+
[`io-sim`]: https://hackage.haskell.org/package/io-sim

si-timers/si-timers.cabal

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,10 @@
11
cabal-version: 3.0
22
name: si-timers
33
version: 1.0.0.0
4-
synopsis: Timers using SI units (seconds) which are safe on 32-bit
5-
platforms.
4+
synopsis: timers using SI units (seconds)
5+
description:
6+
Timers using SI units (seconds) which are safe on 32-bit platforms and
7+
compatible with [io-sim](https://hackage.haskell.org/package/io-sim).
68
license: Apache-2.0
79
license-files:
810
LICENSE

strict-mvar/strict-mvar.cabal

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11
cabal-version: 3.0
22
name: strict-mvar
33
version: 1.0.0.0
4-
synopsis: Strict MVars for implementations of the `io-classes` MVar interface
5-
description: Strict MVars for implementations of the `io-classes` MVar interface.
4+
synopsis: Strict MVars for IO and IOSim
5+
description:
6+
Strict @MVar@ interface compatible with
7+
[IO](https://hackage.haskell.org/package/base-4.18.0.0/docs/Prelude.html#t:IO)
8+
& [io-sim](https://hackage.haskell.org/package/io-sim).
69
license: Apache-2.0
710
license-files:
811
LICENSE
@@ -12,6 +15,8 @@ author: IOHK Engineering Team
1215
maintainer: [email protected]
1316
category: Control
1417
build-type: Simple
18+
extra-source-files: CHANGELOG.md
19+
README.md
1520
tested-with: GHC == { 8.10.7, 9.2.5, 9.4.4 }
1621

1722
source-repository head

strict-stm/strict-stm.cabal

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,11 @@ cabal-version: 3.0
22
name: strict-stm
33
version: 1.0.0.0
44
synopsis: Strict STM interface polymorphic over stm implementation.
5+
description:
6+
Strict STM interface provided on top of
7+
[io-classes](https://hackage.haskell.org/package/io-classes) and thus
8+
compatible with [stm](https://hackage.haskell.org/package/stm)
9+
& [io-sim](https://hackage.haskell.org/package/io-sim).
510
license: Apache-2.0
611
license-files:
712
LICENSE
@@ -67,4 +72,4 @@ library
6772
ghc-options: -fno-ignore-asserts
6873

6974
if flag(checktvarinvariant)
70-
cpp-options: -DCHECK_TVAR_INVARIANT
75+
cpp-options: -DCHECK_TVAR_INVARIAN

0 commit comments

Comments
 (0)