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cpu: use MRS instruction to read arm64 system registers
Use the MRS instruction with the corresponding system register instead of encoding the instructions using a WORD directive. Change-Id: I2995dfa6ad731cb03867160127db84898adfdda5 Reviewed-on: https://go-review.googlesource.com/c/sys/+/583135 LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Michael Knyszek <[email protected]> Reviewed-by: David Chase <[email protected]> Auto-Submit: Tobias Klauser <[email protected]>
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cpu/cpu_arm64.s

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,16 +9,14 @@
99
// func getisar0() uint64
1010
TEXT ·getisar0(SB),NOSPLIT,$0-8
1111
// get Instruction Set Attributes 0 into x0
12-
// mrs x0, ID_AA64ISAR0_EL1 = d5380600
13-
WORD $0xd5380600
12+
MRS ID_AA64ISAR0_EL1, R0
1413
MOVD R0, ret+0(FP)
1514
RET
1615

1716
// func getisar1() uint64
1817
TEXT ·getisar1(SB),NOSPLIT,$0-8
1918
// get Instruction Set Attributes 1 into x0
20-
// mrs x0, ID_AA64ISAR1_EL1 = d5380620
21-
WORD $0xd5380620
19+
MRS ID_AA64ISAR1_EL1, R0
2220
MOVD R0, ret+0(FP)
2321
RET
2422

@@ -33,15 +31,13 @@ TEXT ·getmmfr1(SB),NOSPLIT,$0-8
3331
// func getpfr0() uint64
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TEXT ·getpfr0(SB),NOSPLIT,$0-8
3533
// get Processor Feature Register 0 into x0
36-
// mrs x0, ID_AA64PFR0_EL1 = d5380400
37-
WORD $0xd5380400
34+
MRS ID_AA64PFR0_EL1, R0
3835
MOVD R0, ret+0(FP)
3936
RET
4037

4138
// func getzfr0() uint64
4239
TEXT ·getzfr0(SB),NOSPLIT,$0-8
4340
// get SVE Feature Register 0 into x0
44-
// mrs x0, ID_AA64ZFR0_EL1 = d5380480
45-
WORD $0xd5380480
41+
MRS ID_AA64ZFR0_EL1, R0
4642
MOVD R0, ret+0(FP)
4743
RET

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