Skip to content

cmd/asm: add support for LDREXB/STREXB #69959

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 2 commits into from
Closed

cmd/asm: add support for LDREXB/STREXB #69959

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
d99a3f0
cmd/asm: add support for LDREXB/STREXB
mauri870 Oct 19, 2024
d6a7978
code review changes for registers
mauri870 Oct 21, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion src/cmd/asm/internal/arch/arm.go
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@ func IsARMCMP(op obj.As) bool {
// one of the STREX-like instructions that require special handling.
func IsARMSTREX(op obj.As) bool {
switch op {
case arm.ASTREX, arm.ASTREXD, arm.ASWPW, arm.ASWPBU:
case arm.ASTREX, arm.ASTREXD, arm.ASTREXB, arm.ASWPW, arm.ASWPBU:
return true
}
return false
Expand Down
2 changes: 2 additions & 0 deletions src/cmd/asm/internal/asm/testdata/armerror.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -260,5 +260,7 @@ TEXT errors(SB),$0
STREXD R0, (R2), R1 // ERROR "cannot use same register as both source and destination"
STREXD R0, (R2), R2 // ERROR "cannot use same register as both source and destination"
STREXD R1, (R4), R7 // ERROR "must be even"
STREXB R0, (R2), R0 // ERROR "cannot use same register as both source and destination"
STREXB R0, (R2), R2 // ERROR "cannot use same register as both source and destination"

END
2 changes: 2 additions & 0 deletions src/cmd/asm/internal/asm/testdata/armv6.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,10 @@ TEXT foo(SB), DUPOK|NOSPLIT, $0
MOVDF F4, F5 // c45bb7ee

LDREX (R8), R9 // 9f9f98e1
LDREXB (R11), R12 // 9fcfdbe1
LDREXD (R11), R12 // 9fcfbbe1
STREX R3, (R4), R5 // STREX (R4), R3, R5 // 935f84e1
STREXB R8, (R9), g // STREXB (R9), R8, g // 98afc9e1
STREXD R8, (R9), g // STREXD (R9), R8, g // 98afa9e1

CMPF F8, F9 // c89ab4ee10faf1ee
Expand Down
2 changes: 2 additions & 0 deletions src/cmd/internal/obj/arm/a.out.go
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -333,7 +333,9 @@ const (
ALDREX
ASTREX
ALDREXD
ALDREXB
ASTREXD
ASTREXB

ADMB

Expand Down
2 changes: 2 additions & 0 deletions src/cmd/internal/obj/arm/anames.go
View file
Open in desktop

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

34 changes: 26 additions & 8 deletions src/cmd/internal/obj/arm/asm5.go
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,9 @@ var optab = []Optab{
{AMOVW, C_REG, C_NONE, C_FREG, 88, 4, 0, 0, 0, 0},
{AMOVW, C_FREG, C_NONE, C_REG, 89, 4, 0, 0, 0, 0},
{ALDREXD, C_SOREG, C_NONE, C_REG, 91, 4, 0, 0, 0, 0},
{ALDREXB, C_SOREG, C_NONE, C_REG, 91, 4, 0, 0, 0, 0},
{ASTREXD, C_SOREG, C_REG, C_REG, 92, 4, 0, 0, 0, 0},
{ASTREXB, C_SOREG, C_REG, C_REG, 92, 4, 0, 0, 0, 0},
{APLD, C_SOREG, C_NONE, C_NONE, 95, 4, 0, 0, 0, 0},
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, 96, 4, 0, 0, 0, 0},
{ACLZ, C_REG, C_NONE, C_REG, 97, 4, 0, 0, 0, 0},
Expand Down Expand Up @@ -1432,7 +1434,9 @@ func buildop(ctxt *obj.Link) {
case ALDREX,
ASTREX,
ALDREXD,
ALDREXB,
ASTREXD,
ASTREXB,
ADMB,
APLD,
AAND,
Expand Down Expand Up @@ -2397,30 +2401,44 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) {
o1 |= (uint32(p.From.Reg) & 15) << 16
o1 |= (uint32(p.To.Reg) & 15) << 12

case 91: /* ldrexd oreg,reg */
case 91: /* ldrexd/ldrexb oreg,reg */
c.aclass(&p.From)

if c.instoffset != 0 {
c.ctxt.Diag("offset must be zero in LDREX")
}
o1 = 0x1b<<20 | 0xf9f

switch p.As {
case ALDREXD:
o1 = 0x1b << 20
case ALDREXB:
o1 = 0x1d << 20
}
o1 |= 0xf9f
o1 |= (uint32(p.From.Reg) & 15) << 16
o1 |= (uint32(p.To.Reg) & 15) << 12
o1 |= ((uint32(p.Scond) & C_SCOND) ^ C_SCOND_XOR) << 28

case 92: /* strexd reg,oreg,reg */
case 92: /* strexd/strexb reg,oreg,reg */
c.aclass(&p.From)

if c.instoffset != 0 {
c.ctxt.Diag("offset must be zero in STREX")
}
if p.Reg&1 != 0 {
c.ctxt.Diag("source register must be even in STREXD: %v", p)
}
if p.To.Reg == p.From.Reg || p.To.Reg == p.Reg || p.To.Reg == p.Reg+1 {
if p.To.Reg == p.From.Reg || p.To.Reg == p.Reg || (p.As == ASTREXD && p.To.Reg == p.Reg+1) {
c.ctxt.Diag("cannot use same register as both source and destination: %v", p)
}
o1 = 0x1a<<20 | 0xf90

switch p.As {
case ASTREXD:
if p.Reg&1 != 0 {
c.ctxt.Diag("source register must be even in STREXD: %v", p)
}
o1 = 0x1a << 20
case ASTREXB:
o1 = 0x1c << 20
}
o1 |= 0xf90
o1 |= (uint32(p.From.Reg) & 15) << 16
o1 |= (uint32(p.Reg) & 15) << 0
o1 |= (uint32(p.To.Reg) & 15) << 12
Expand Down