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[dev.ssa] cmd/compile: PPC: FP load/store/const/cmp/neg; div/mod
FP<->int conversions remain. Updates #16010. Change-Id: I38d7a4923e34d0a489935fffc4c96c020cafdba2 Reviewed-on: https://go-review.googlesource.com/25589 Run-TryBot: David Chase <[email protected]> TryBot-Result: Gobot Gobot <[email protected]> Reviewed-by: Keith Randall <[email protected]>
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6 files changed

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-36
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6 files changed

+565
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‎src/cmd/compile/internal/ppc64/prog.go

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@ var progtable = [ppc64.ALAST & obj.AMask]obj.ProgInfo{
5858
ppc64.AMULHDU & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite},
5959
ppc64.ADIVD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
6060
ppc64.ADIVDU & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
61+
ppc64.ADIVW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite},
62+
ppc64.ADIVWU & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite},
6163
ppc64.ASLD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
6264
ppc64.ASRD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
6365
ppc64.ASRAD & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
@@ -85,6 +87,7 @@ var progtable = [ppc64.ALAST & obj.AMask]obj.ProgInfo{
8587
ppc64.AFCMPU & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RightRead},
8688
ppc64.AFRSP & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv},
8789
ppc64.AFSQRT & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite},
90+
ppc64.AFNEG & obj.AMask: {Flags: gc.SizeD | gc.LeftRead | gc.RightWrite},
8891

8992
// Moves
9093
ppc64.AMOVB & obj.AMask: {Flags: gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv},

‎src/cmd/compile/internal/ppc64/ssa.go

Lines changed: 90 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ import (
99
"cmd/compile/internal/ssa"
1010
"cmd/internal/obj"
1111
"cmd/internal/obj/ppc64"
12+
"math"
1213
)
1314

1415
var ssaRegToReg = []int16{
@@ -265,8 +266,85 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
265266
p.To.Name = obj.NAME_AUTO
266267
}
267268

269+
case ssa.OpPPC64DIVD:
270+
// For now,
271+
//
272+
// cmp arg1, -1
273+
// be ahead
274+
// v = arg0 / arg1
275+
// b over
276+
// ahead: v = - arg0
277+
// over: nop
278+
r := gc.SSARegNum(v)
279+
r0 := gc.SSARegNum(v.Args[0])
280+
r1 := gc.SSARegNum(v.Args[1])
281+
282+
p := gc.Prog(ppc64.ACMP)
283+
p.From.Type = obj.TYPE_REG
284+
p.From.Reg = r1
285+
p.To.Type = obj.TYPE_CONST
286+
p.To.Offset = -1
287+
288+
pbahead := gc.Prog(ppc64.ABEQ)
289+
pbahead.To.Type = obj.TYPE_BRANCH
290+
291+
p = gc.Prog(v.Op.Asm())
292+
p.From.Type = obj.TYPE_REG
293+
p.From.Reg = r1
294+
p.Reg = r0
295+
p.To.Type = obj.TYPE_REG
296+
p.To.Reg = r
297+
298+
pbover := gc.Prog(obj.AJMP)
299+
pbover.To.Type = obj.TYPE_BRANCH
300+
301+
p = gc.Prog(ppc64.ANEG)
302+
p.To.Type = obj.TYPE_REG
303+
p.To.Reg = r
304+
p.From.Type = obj.TYPE_REG
305+
p.From.Reg = r0
306+
gc.Patch(pbahead, p)
307+
308+
p = gc.Prog(obj.ANOP)
309+
gc.Patch(pbover, p)
310+
311+
case ssa.OpPPC64DIVW:
312+
// word-width version of above
313+
r := gc.SSARegNum(v)
314+
r0 := gc.SSARegNum(v.Args[0])
315+
r1 := gc.SSARegNum(v.Args[1])
316+
317+
p := gc.Prog(ppc64.ACMPW)
318+
p.From.Type = obj.TYPE_REG
319+
p.From.Reg = r1
320+
p.To.Type = obj.TYPE_CONST
321+
p.To.Offset = -1
322+
323+
pbahead := gc.Prog(ppc64.ABEQ)
324+
pbahead.To.Type = obj.TYPE_BRANCH
325+
326+
p = gc.Prog(v.Op.Asm())
327+
p.From.Type = obj.TYPE_REG
328+
p.From.Reg = r1
329+
p.Reg = r0
330+
p.To.Type = obj.TYPE_REG
331+
p.To.Reg = r
332+
333+
pbover := gc.Prog(obj.AJMP)
334+
pbover.To.Type = obj.TYPE_BRANCH
335+
336+
p = gc.Prog(ppc64.ANEG)
337+
p.To.Type = obj.TYPE_REG
338+
p.To.Reg = r
339+
p.From.Type = obj.TYPE_REG
340+
p.From.Reg = r0
341+
gc.Patch(pbahead, p)
342+
343+
p = gc.Prog(obj.ANOP)
344+
gc.Patch(pbover, p)
345+
268346
case ssa.OpPPC64ADD, ssa.OpPPC64FADD, ssa.OpPPC64FADDS, ssa.OpPPC64SUB, ssa.OpPPC64FSUB, ssa.OpPPC64FSUBS,
269-
ssa.OpPPC64MULLD, ssa.OpPPC64MULLW, ssa.OpPPC64DIVD, ssa.OpPPC64DIVW, ssa.OpPPC64DIVDU, ssa.OpPPC64DIVWU,
347+
ssa.OpPPC64MULLD, ssa.OpPPC64MULLW, ssa.OpPPC64DIVDU, ssa.OpPPC64DIVWU,
270348
ssa.OpPPC64SRAD, ssa.OpPPC64SRAW, ssa.OpPPC64SRD, ssa.OpPPC64SRW, ssa.OpPPC64SLD, ssa.OpPPC64SLW,
271349
ssa.OpPPC64MULHD, ssa.OpPPC64MULHW, ssa.OpPPC64MULHDU, ssa.OpPPC64MULHWU,
272350
ssa.OpPPC64FMUL, ssa.OpPPC64FMULS, ssa.OpPPC64FDIV, ssa.OpPPC64FDIVS,
@@ -298,14 +376,13 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
298376
p.To.Type = obj.TYPE_REG
299377
p.To.Reg = ppc64.REGTMP // Ignored; this is for the carry effect.
300378

301-
case ssa.OpPPC64NEG:
379+
case ssa.OpPPC64NEG, ssa.OpPPC64FNEG:
302380
r := gc.SSARegNum(v)
303381
p := gc.Prog(v.Op.Asm())
304-
if r != gc.SSARegNum(v.Args[0]) {
305-
v.Fatalf("input[0] and output not in same register %s", v.LongString())
306-
}
307382
p.To.Type = obj.TYPE_REG
308383
p.To.Reg = r
384+
p.From.Type = obj.TYPE_REG
385+
p.From.Reg = gc.SSARegNum(v.Args[0])
309386

310387
case ssa.OpPPC64ADDconst, ssa.OpPPC64ANDconst, ssa.OpPPC64ORconst, ssa.OpPPC64XORconst,
311388
ssa.OpPPC64SRADconst, ssa.OpPPC64SRAWconst, ssa.OpPPC64SRDconst, ssa.OpPPC64SRWconst, ssa.OpPPC64SLDconst, ssa.OpPPC64SLWconst:
@@ -355,13 +432,20 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
355432
v.Fatalf("bad reg %s for symbol type %T, want %s", reg.Name(), v.Aux, wantreg)
356433
}
357434

358-
case ssa.OpPPC64MOVDconst, ssa.OpPPC64MOVWconst, ssa.OpPPC64FMOVDconst, ssa.OpPPC64FMOVSconst:
435+
case ssa.OpPPC64MOVDconst, ssa.OpPPC64MOVWconst:
359436
p := gc.Prog(v.Op.Asm())
360437
p.From.Type = obj.TYPE_CONST
361438
p.From.Offset = v.AuxInt
362439
p.To.Type = obj.TYPE_REG
363440
p.To.Reg = gc.SSARegNum(v)
364441

442+
case ssa.OpPPC64FMOVDconst, ssa.OpPPC64FMOVSconst:
443+
p := gc.Prog(v.Op.Asm())
444+
p.From.Type = obj.TYPE_FCONST
445+
p.From.Val = math.Float64frombits(uint64(v.AuxInt))
446+
p.To.Type = obj.TYPE_REG
447+
p.To.Reg = gc.SSARegNum(v)
448+
365449
case ssa.OpPPC64FCMPU, ssa.OpPPC64CMP, ssa.OpPPC64CMPW, ssa.OpPPC64CMPU, ssa.OpPPC64CMPWU:
366450
p := gc.Prog(v.Op.Asm())
367451
p.From.Type = obj.TYPE_REG

‎src/cmd/compile/internal/ssa/gen/PPC64.rules

Lines changed: 30 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,15 @@
1919
(Sub32F x y) -> (FSUBS x y)
2020
(Sub64F x y) -> (FSUB x y)
2121

22+
(Mod16 x y) -> (Mod32 (SignExt16to32 x) (SignExt16to32 y))
23+
(Mod16u x y) -> (Mod32u (ZeroExt16to32 x) (ZeroExt16to32 y))
24+
(Mod8 x y) -> (Mod32 (SignExt8to32 x) (SignExt8to32 y))
25+
(Mod8u x y) -> (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
26+
(Mod64 x y) -> (SUB x (MULLD y (DIVD x y)))
27+
(Mod64u x y) -> (SUB x (MULLD y (DIVDU x y)))
28+
(Mod32 x y) -> (SUB x (MULLW y (DIVW x y)))
29+
(Mod32u x y) -> (SUB x (MULLW y (DIVWU x y)))
30+
2231
(Mul64 x y) -> (MULLD x y)
2332
(Mul32 x y) -> (MULLW x y)
2433
(Mul16 x y) -> (MULLW x y)
@@ -115,7 +124,6 @@
115124
(Rsh8Ux8 x y) -> (SRW (ZeroExt8to32 x) (ORN y <config.fe.TypeInt64()> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y)))))
116125
(Lsh8x8 x y) -> (SLW x (ORN y <config.fe.TypeInt64()> (MaskIfNotCarry (ADDconstForCarry [-8] (ZeroExt8to64 y)))))
117126

118-
119127
// Potentially useful optimizing rewrites.
120128
// (ADDconstForCarry [k] c), k < 0 && (c < 0 || k+c >= 0) -> CarrySet
121129
// (ADDconstForCarry [k] c), K < 0 && (c >= 0 && k+c < 0) -> CarryClear
@@ -151,6 +159,8 @@
151159
(Xor16 x y) -> (XOR x y)
152160
(Xor8 x y) -> (XOR x y)
153161

162+
(Neg64F x) -> (FNEG x)
163+
(Neg32F x) -> (FNEG x)
154164
(Neg64 x) -> (NEG x)
155165
(Neg32 x) -> (NEG x)
156166
(Neg16 x) -> (NEG x)
@@ -172,19 +182,25 @@
172182
(Eq16 x y) -> (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
173183
(Eq32 x y) -> (Equal (CMPW x y))
174184
(Eq64 x y) -> (Equal (CMP x y))
185+
(Eq32F x y) -> (Equal (FCMPU x y))
186+
(Eq64F x y) -> (Equal (FCMPU x y))
175187
(EqPtr x y) -> (Equal (CMP x y))
176188

177189
(NeqB x y) -> (XOR x y)
178190
(Neq8 x y) -> (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
179191
(Neq16 x y) -> (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
180192
(Neq32 x y) -> (NotEqual (CMPW x y))
181193
(Neq64 x y) -> (NotEqual (CMP x y))
194+
(Neq32F x y) -> (NotEqual (FCMPU x y))
195+
(Neq64F x y) -> (NotEqual (FCMPU x y))
182196
(NeqPtr x y) -> (NotEqual (CMP x y))
183197

184198
(Less8 x y) -> (LessThan (CMPW (SignExt8to32 x) (SignExt8to32 y)))
185199
(Less16 x y) -> (LessThan (CMPW (SignExt16to32 x) (SignExt16to32 y)))
186200
(Less32 x y) -> (LessThan (CMPW x y))
187201
(Less64 x y) -> (LessThan (CMP x y))
202+
(Less32F x y) -> (LessThan (FCMPU x y))
203+
(Less64F x y) -> (LessThan (FCMPU x y))
188204

189205
(Less8U x y) -> (LessThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y)))
190206
(Less16U x y) -> (LessThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y)))
@@ -195,6 +211,8 @@
195211
(Leq16 x y) -> (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y)))
196212
(Leq32 x y) -> (LessEqual (CMPW x y))
197213
(Leq64 x y) -> (LessEqual (CMP x y))
214+
(Leq32F x y) -> (LessEqual (FCMPU x y))
215+
(Leq64F x y) -> (LessEqual (FCMPU x y))
198216

199217
(Leq8U x y) -> (LessEqual (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y)))
200218
(Leq16U x y) -> (LessEqual (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y)))
@@ -205,6 +223,8 @@
205223
(Greater16 x y) -> (GreaterThan (CMPW (SignExt16to32 x) (SignExt16to32 y)))
206224
(Greater32 x y) -> (GreaterThan (CMPW x y))
207225
(Greater64 x y) -> (GreaterThan (CMP x y))
226+
(Greater32F x y) -> (GreaterThan (FCMPU x y))
227+
(Greater64F x y) -> (GreaterThan (FCMPU x y))
208228

209229
(Greater8U x y) -> (GreaterThan (CMPWU (ZeroExt8to32 x) (ZeroExt8to32 y)))
210230
(Greater16U x y) -> (GreaterThan (CMPWU (ZeroExt16to32 x) (ZeroExt16to32 y)))
@@ -215,20 +235,14 @@
215235
(Geq16 x y) -> (GreaterEqual (CMPW (SignExt16to32 x) (SignExt16to32 y)))
216236
(Geq32 x y) -> (GreaterEqual (CMPW x y))
217237
(Geq64 x y) -> (GreaterEqual (CMP x y))
238+
(Geq32F x y) -> (GreaterEqual (FCMPU x y))
239+
(Geq64F x y) -> (GreaterEqual (FCMPU x y))
218240

219241
(Geq8U x y) -> (GreaterEqual (CMPU (ZeroExt8to32 x) (ZeroExt8to32 y)))
220242
(Geq16U x y) -> (GreaterEqual (CMPU (ZeroExt16to32 x) (ZeroExt16to32 y)))
221243
(Geq32U x y) -> (GreaterEqual (CMPU x y))
222244
(Geq64U x y) -> (GreaterEqual (CMPU x y))
223245

224-
(Less64F x y) -> (LessThan (FCMPU x y))
225-
226-
(Leq64F x y) -> (LessEqual (FCMPU x y)) // ??
227-
228-
(Eq64F x y) -> (Equal (FCMPU x y))
229-
230-
(Neq64F x y) -> (NotEqual (FCMPU x y))
231-
232246
// Absorb pseudo-ops into blocks.
233247
(If (Equal cc) yes no) -> (EQ cc yes no)
234248
(If (NotEqual cc) yes no) -> (NE cc yes no)
@@ -345,11 +359,14 @@
345359
(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem)
346360
(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && isSigned(t))) -> (MOVBload ptr mem)
347361
(Load <t> ptr mem) && is8BitInt(t) && !isSigned(t) -> (MOVBZload ptr mem)
362+
348363
(Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem)
349364
(Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem)
350365

351-
(Store [8] ptr val mem) -> (MOVDstore ptr val mem)
352-
(Store [4] ptr val mem) -> (MOVWstore ptr val mem)
366+
(Store [8] ptr val mem) && is64BitFloat(val.Type) -> (FMOVDstore ptr val mem)
367+
(Store [4] ptr val mem) && is32BitFloat(val.Type) -> (FMOVSstore ptr val mem)
368+
(Store [8] ptr val mem) && (is64BitInt(val.Type) || isPtr(val.Type)) -> (MOVDstore ptr val mem)
369+
(Store [4] ptr val mem) && is32BitInt(val.Type) -> (MOVWstore ptr val mem)
353370
(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
354371
(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
355372

@@ -470,8 +487,8 @@
470487

471488
// Optimizations
472489

473-
(ADD (MOVDconst [c]) x) -> (ADDconst [c] x)
474-
(ADD x (MOVDconst [c])) -> (ADDconst [c] x)
490+
(ADD (MOVDconst [c]) x) && int64(int32(c)) == c -> (ADDconst [c] x)
491+
(ADD x (MOVDconst [c])) && int64(int32(c)) == c -> (ADDconst [c] x)
475492

476493
// Fold offsets for stores.
477494
(MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} x val mem)

‎src/cmd/compile/internal/ssa/gen/PPC64Ops.go

Lines changed: 16 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -141,12 +141,12 @@ func init() {
141141
gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}}
142142
gpstorezero = regInfo{inputs: []regMask{gp | sp | sb}} // ppc64.REGZERO is reserved zero value
143143
fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
144-
// fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
145-
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
146-
fp2cr = regInfo{inputs: []regMask{fp, fp}}
147-
fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}}
148-
fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}}
149-
callerSave = regMask(gp | fp)
144+
fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
145+
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
146+
fp2cr = regInfo{inputs: []regMask{fp, fp}}
147+
fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}}
148+
fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}}
149+
callerSave = regMask(gp | fp)
150150
)
151151
ops := []opData{
152152
{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
@@ -157,8 +157,8 @@ func init() {
157157
{name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"}, // arg0-arg1
158158
{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"}, // arg0-arg1
159159

160-
{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", commutative: true}, // arg0*arg1 (signed 64-bit)
161-
{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", commutative: true}, // arg0*arg1 (signed 32-bit)
160+
{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true}, // arg0*arg1 (signed 64-bit)
161+
{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true}, // arg0*arg1 (signed 32-bit)
162162

163163
{name: "MULHD", argLength: 2, reg: gp21, asm: "MULHD", commutative: true}, // (arg0 * arg1) >> 64, signed
164164
{name: "MULHW", argLength: 2, reg: gp21, asm: "MULHW", commutative: true}, // (arg0 * arg1) >> 32, signed
@@ -188,18 +188,21 @@ func init() {
188188
{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"}, // arg0/arg1
189189
{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1
190190

191-
{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD"}, // arg0/arg1 (signed 64-bit)
192-
{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW"}, // arg0/arg1 (signed 32-bit)
193-
{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU"}, // arg0/arg1 (unsigned 64-bit)
194-
{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU"}, // arg0/arg1 (unsigned 32-bit)
191+
{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"}, // arg0/arg1 (signed 64-bit)
192+
{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"}, // arg0/arg1 (signed 32-bit)
193+
{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
194+
{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"}, // arg0/arg1 (unsigned 32-bit)
195+
196+
// MOD is implemented as rem := arg0 - (arg0/arg1) * arg1
195197

196198
{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0&arg1
197199
{name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"}, // arg0&^arg1
198200
{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0|arg1
199201
{name: "ORN", argLength: 2, reg: gp21, asm: "ORN"}, // arg0|^arg1
200202
{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true}, // arg0^arg1
201203
{name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true}, // arg0^^arg1
202-
{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0
204+
{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"}, // -arg0 (integer)
205+
{name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG"}, // -arg0 (floating point)
203206

204207
{name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0|aux
205208
{name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"}, // arg0^aux

‎src/cmd/compile/internal/ssa/opGen.go

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -969,6 +969,7 @@ const (
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OpPPC64XOR
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OpPPC64EQV
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OpPPC64NEG
972+
OpPPC64FNEG
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OpPPC64ORconst
973974
OpPPC64XORconst
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OpPPC64ANDconst
@@ -11957,6 +11958,19 @@ var opcodeTable = [...]opInfo{
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},
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},
1195911960
},
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{
11962+
name: "FNEG",
11963+
argLen: 1,
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asm: ppc64.AFNEG,
11965+
reg: regInfo{
11966+
inputs: []inputInfo{
11967+
{0, 9223372032559808512}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
11968+
},
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outputs: []outputInfo{
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{0, 9223372032559808512}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
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},
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},
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},
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{
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name: "ORconst",
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auxType: auxInt64,

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