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randall77randall77
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cmd/compile: replace isSigned(t) with t.IsSigned()
No change in semantics, just removing an unneeded helper. Also align rules a bit. Change-Id: Ie4dabb99392315a7700c645b3d0931eb8766a5fa Reviewed-on: https://go-review.googlesource.com/c/go/+/483439 Reviewed-by: David Chase <[email protected]> Run-TryBot: Keith Randall <[email protected]> TryBot-Result: Gopher Robot <[email protected]> Reviewed-by: Keith Randall <[email protected]>
1 parent 60140a8 commit a3f3868

19 files changed

+197
-201
lines changed

‎src/cmd/compile/internal/ssa/_gen/386.rules

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -206,8 +206,8 @@
206206
(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
207207

208208
// Lowering stores
209-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
210-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
209+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
210+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
211211
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
212212
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
213213
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)

‎src/cmd/compile/internal/ssa/_gen/AMD64.rules

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -234,8 +234,8 @@
234234
(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
235235

236236
// Lowering stores
237-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
238-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
237+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
238+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
239239
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
240240
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
241241
(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)

‎src/cmd/compile/internal/ssa/_gen/ARM.rules

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -253,10 +253,10 @@
253253

254254
// loads
255255
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
256-
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
257-
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
258-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
259-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
256+
(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
257+
(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
258+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
259+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
260260
(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
261261
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
262262
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
@@ -265,8 +265,8 @@
265265
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
266266
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
267267
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
268-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
269-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
268+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
269+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
270270

271271
// zero instructions
272272
(Zero [0] _ mem) => mem

‎src/cmd/compile/internal/ssa/_gen/ARM64.rules

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -327,12 +327,12 @@
327327

328328
// loads
329329
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
330-
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
331-
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
332-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
333-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
334-
(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
335-
(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
330+
(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
331+
(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
332+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
333+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
334+
(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
335+
(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
336336
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
337337
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
338338
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
@@ -342,8 +342,8 @@
342342
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
343343
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
344344
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
345-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
346-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
345+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
346+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
347347

348348
// zeroing
349349
(Zero [0] _ mem) => mem

‎src/cmd/compile/internal/ssa/_gen/LOONG64.rules

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -233,12 +233,12 @@
233233

234234
// loads
235235
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
236-
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
237-
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
238-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
239-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
240-
(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
241-
(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
236+
(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
237+
(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
238+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
239+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
240+
(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
241+
(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
242242
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
243243
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
244244
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
@@ -248,8 +248,8 @@
248248
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
249249
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
250250
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
251-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
252-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
251+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
252+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
253253

254254
// zeroing
255255
(Zero [0] _ mem) => mem

‎src/cmd/compile/internal/ssa/_gen/MIPS.rules

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -215,10 +215,10 @@
215215

216216
// loads
217217
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
218-
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
219-
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
220-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
221-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
218+
(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
219+
(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
220+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
221+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
222222
(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
223223
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
224224
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
@@ -227,8 +227,8 @@
227227
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
228228
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
229229
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
230-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
231-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
230+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
231+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
232232

233233
// zero instructions
234234
(Zero [0] _ mem) => mem

‎src/cmd/compile/internal/ssa/_gen/MIPS64.rules

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -224,12 +224,12 @@
224224

225225
// loads
226226
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
227-
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
228-
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
229-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
230-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
231-
(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
232-
(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
227+
(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
228+
(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
229+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
230+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
231+
(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
232+
(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
233233
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
234234
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
235235
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
@@ -239,8 +239,8 @@
239239
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
240240
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
241241
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
242-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
243-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
242+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
243+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
244244

245245
// zeroing
246246
(Zero [0] _ mem) => mem

‎src/cmd/compile/internal/ssa/_gen/PPC64.rules

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -84,11 +84,11 @@
8484
(ZeroExt16to(32|64) ...) => (MOVHZreg ...)
8585
(ZeroExt32to64 ...) => (MOVWZreg ...)
8686

87-
(Trunc(16|32|64)to8 <t> x) && isSigned(t) => (MOVBreg x)
87+
(Trunc(16|32|64)to8 <t> x) && t.IsSigned() => (MOVBreg x)
8888
(Trunc(16|32|64)to8 x) => (MOVBZreg x)
89-
(Trunc(32|64)to16 <t> x) && isSigned(t) => (MOVHreg x)
89+
(Trunc(32|64)to16 <t> x) && t.IsSigned() => (MOVHreg x)
9090
(Trunc(32|64)to16 x) => (MOVHZreg x)
91-
(Trunc64to32 <t> x) && isSigned(t) => (MOVWreg x)
91+
(Trunc64to32 <t> x) && t.IsSigned() => (MOVWreg x)
9292
(Trunc64to32 x) => (MOVWZreg x)
9393

9494
// Lowering constants
@@ -274,14 +274,14 @@
274274
// Lowering comparisons
275275
(EqB x y) => (Select0 <typ.Int> (ANDCCconst [1] (EQV x y)))
276276
// Sign extension dependence on operand sign sets up for sign/zero-extension elision later
277-
(Eq(8|16) x y) && isSigned(x.Type) && isSigned(y.Type) => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
277+
(Eq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (Equal (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
278278
(Eq(8|16) x y) => (Equal (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
279279
(Eq(32|64|Ptr) x y) => (Equal ((CMPW|CMP|CMP) x y))
280280
(Eq(32|64)F x y) => (Equal (FCMPU x y))
281281

282282
(NeqB ...) => (XOR ...)
283283
// Like Eq8 and Eq16, prefer sign extension likely to enable later elision.
284-
(Neq(8|16) x y) && isSigned(x.Type) && isSigned(y.Type) => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
284+
(Neq(8|16) x y) && x.Type.IsSigned() && y.Type.IsSigned() => (NotEqual (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
285285
(Neq(8|16) x y) => (NotEqual (CMPW (ZeroExt(8|16)to32 x) (ZeroExt(8|16)to32 y)))
286286
(Neq(32|64|Ptr) x y) => (NotEqual ((CMPW|CMP|CMP) x y))
287287
(Neq(32|64)F x y) => (NotEqual (FCMPU x y))
@@ -419,19 +419,19 @@
419419

420420
// Lowering loads
421421
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
422-
(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) => (MOVWload ptr mem)
423-
(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) => (MOVWZload ptr mem)
424-
(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) => (MOVHload ptr mem)
425-
(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) => (MOVHZload ptr mem)
422+
(Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
423+
(Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
424+
(Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
425+
(Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
426426
(Load <t> ptr mem) && t.IsBoolean() => (MOVBZload ptr mem)
427-
(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
428-
(Load <t> ptr mem) && is8BitInt(t) && !isSigned(t) => (MOVBZload ptr mem)
427+
(Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBreg (MOVBZload ptr mem)) // PPC has no signed-byte load.
428+
(Load <t> ptr mem) && is8BitInt(t) && !t.IsSigned() => (MOVBZload ptr mem)
429429

430430
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
431431
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
432432

433-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
434-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
433+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
434+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
435435
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
436436
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
437437
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
@@ -804,12 +804,12 @@
804804
(MOV(B|W)Zreg x:(Select0 (LoweredAtomicLoad(8|32) _ _))) => x
805805

806806
// don't extend if argument is already extended
807-
(MOVBreg x:(Arg <t>)) && is8BitInt(t) && isSigned(t) => x
808-
(MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !isSigned(t) => x
809-
(MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && isSigned(t) => x
810-
(MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !isSigned(t) => x
811-
(MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && isSigned(t) => x
812-
(MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !isSigned(t) => x
807+
(MOVBreg x:(Arg <t>)) && is8BitInt(t) && t.IsSigned() => x
808+
(MOVBZreg x:(Arg <t>)) && is8BitInt(t) && !t.IsSigned() => x
809+
(MOVHreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && t.IsSigned() => x
810+
(MOVHZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t)) && !t.IsSigned() => x
811+
(MOVWreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && t.IsSigned() => x
812+
(MOVWZreg x:(Arg <t>)) && (is8BitInt(t) || is16BitInt(t) || is32BitInt(t)) && !t.IsSigned() => x
813813

814814
(MOVBZreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
815815
(MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])

‎src/cmd/compile/internal/ssa/_gen/RISCV64.rules

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -282,16 +282,16 @@
282282
(Neq32F ...) => (FNES ...)
283283

284284
// Loads
285-
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
286-
(Load <t> ptr mem) && ( is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
287-
(Load <t> ptr mem) && ( is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
288-
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
289-
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
290-
(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
291-
(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
292-
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
293-
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVWload ptr mem)
294-
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
285+
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
286+
(Load <t> ptr mem) && ( is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
287+
(Load <t> ptr mem) && ( is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
288+
(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
289+
(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
290+
(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
291+
(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
292+
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
293+
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVWload ptr mem)
294+
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
295295

296296
// Stores
297297
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)

‎src/cmd/compile/internal/ssa/_gen/S390X.rules

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -336,18 +336,18 @@
336336

337337
// Lowering loads
338338
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
339-
(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) => (MOVWload ptr mem)
340-
(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) => (MOVWZload ptr mem)
341-
(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) => (MOVHload ptr mem)
342-
(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) => (MOVHZload ptr mem)
343-
(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) => (MOVBload ptr mem)
344-
(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) => (MOVBZload ptr mem)
339+
(Load <t> ptr mem) && is32BitInt(t) && t.IsSigned() => (MOVWload ptr mem)
340+
(Load <t> ptr mem) && is32BitInt(t) && !t.IsSigned() => (MOVWZload ptr mem)
341+
(Load <t> ptr mem) && is16BitInt(t) && t.IsSigned() => (MOVHload ptr mem)
342+
(Load <t> ptr mem) && is16BitInt(t) && !t.IsSigned() => (MOVHZload ptr mem)
343+
(Load <t> ptr mem) && is8BitInt(t) && t.IsSigned() => (MOVBload ptr mem)
344+
(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !t.IsSigned())) => (MOVBZload ptr mem)
345345
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
346346
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
347347

348348
// Lowering stores
349-
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
350-
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
349+
(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
350+
(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
351351
(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
352352
(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
353353
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)

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