@@ -24,114 +24,114 @@ const (
2424//
2525// The table is formatted for 8-space tabs.
2626var progtable = [arm .ALAST ]obj.ProgInfo {
27- obj .ATYPE : {gc .Pseudo | gc .Skip , 0 , 0 , 0 },
28- obj .ATEXT : {gc .Pseudo , 0 , 0 , 0 },
29- obj .AFUNCDATA : {gc .Pseudo , 0 , 0 , 0 },
30- obj .APCDATA : {gc .Pseudo , 0 , 0 , 0 },
31- obj .AUNDEF : {gc .Break , 0 , 0 , 0 },
32- obj .AUSEFIELD : {gc .OK , 0 , 0 , 0 },
33- obj .ACHECKNIL : {gc .LeftRead , 0 , 0 , 0 },
34- obj .AVARDEF : {gc .Pseudo | gc .RightWrite , 0 , 0 , 0 },
35- obj .AVARKILL : {gc .Pseudo | gc .RightWrite , 0 , 0 , 0 },
27+ obj .ATYPE : {Flags : gc .Pseudo | gc .Skip },
28+ obj .ATEXT : {Flags : gc .Pseudo },
29+ obj .AFUNCDATA : {Flags : gc .Pseudo },
30+ obj .APCDATA : {Flags : gc .Pseudo },
31+ obj .AUNDEF : {Flags : gc .Break },
32+ obj .AUSEFIELD : {Flags : gc .OK },
33+ obj .ACHECKNIL : {Flags : gc .LeftRead },
34+ obj .AVARDEF : {Flags : gc .Pseudo | gc .RightWrite },
35+ obj .AVARKILL : {Flags : gc .Pseudo | gc .RightWrite },
3636
3737 // NOP is an internal no-op that also stands
3838 // for USED and SET annotations, not the Intel opcode.
39- obj .ANOP : {gc .LeftRead | gc .RightWrite , 0 , 0 , 0 },
39+ obj .ANOP : {Flags : gc .LeftRead | gc .RightWrite },
4040
4141 // Integer.
42- arm .AADC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
43- arm .AADD : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
44- arm .AAND : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
45- arm .ABIC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
46- arm .ACMN : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
47- arm .ACMP : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
48- arm .ADIVU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
49- arm .ADIV : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
50- arm .AEOR : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
51- arm .AMODU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
52- arm .AMOD : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
53- arm .AMULALU : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
54- arm .AMULAL : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
55- arm .AMULA : {gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr , 0 , 0 , 0 },
56- arm .AMULU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
57- arm .AMUL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
58- arm .AMULL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
59- arm .AMULLU : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
60- arm .AMVN : {gc .SizeL | gc .LeftRead | gc .RightWrite , 0 , 0 , 0 },
61- arm .AORR : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
62- arm .ARSB : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
63- arm .ARSC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
64- arm .ASBC : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
65- arm .ASLL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
66- arm .ASRA : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
67- arm .ASRL : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
68- arm .ASUB : {gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite , 0 , 0 , 0 },
69- arm .ATEQ : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
70- arm .ATST : {gc .SizeL | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
42+ arm .AADC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
43+ arm .AADD : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
44+ arm .AAND : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
45+ arm .ABIC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
46+ arm .ACMN : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
47+ arm .ACMP : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
48+ arm .ADIVU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
49+ arm .ADIV : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
50+ arm .AEOR : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
51+ arm .AMODU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
52+ arm .AMOD : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
53+ arm .AMULALU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
54+ arm .AMULAL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
55+ arm .AMULA : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | RightRdwr },
56+ arm .AMULU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
57+ arm .AMUL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
58+ arm .AMULL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
59+ arm .AMULLU : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
60+ arm .AMVN : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite },
61+ arm .AORR : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
62+ arm .ARSB : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
63+ arm .ARSC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
64+ arm .ASBC : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
65+ arm .ASLL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
66+ arm .ASRA : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
67+ arm .ASRL : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
68+ arm .ASUB : {Flags : gc .SizeL | gc .LeftRead | gc .RegRead | gc .RightWrite },
69+ arm .ATEQ : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
70+ arm .ATST : {Flags : gc .SizeL | gc .LeftRead | gc .RightRead },
7171
7272 // Floating point.
73- arm .AADDD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
74- arm .AADDF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
75- arm .ACMPD : {gc .SizeD | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
76- arm .ACMPF : {gc .SizeF | gc .LeftRead | gc .RightRead , 0 , 0 , 0 },
77- arm .ADIVD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
78- arm .ADIVF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
79- arm .AMULD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
80- arm .AMULF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
81- arm .ASUBD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
82- arm .ASUBF : {gc .SizeF | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
83- arm .ASQRTD : {gc .SizeD | gc .LeftRead | RightRdwr , 0 , 0 , 0 },
73+ arm .AADDD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
74+ arm .AADDF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
75+ arm .ACMPD : {Flags : gc .SizeD | gc .LeftRead | gc .RightRead },
76+ arm .ACMPF : {Flags : gc .SizeF | gc .LeftRead | gc .RightRead },
77+ arm .ADIVD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
78+ arm .ADIVF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
79+ arm .AMULD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
80+ arm .AMULF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
81+ arm .ASUBD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
82+ arm .ASUBF : {Flags : gc .SizeF | gc .LeftRead | RightRdwr },
83+ arm .ASQRTD : {Flags : gc .SizeD | gc .LeftRead | RightRdwr },
8484
8585 // Conversions.
86- arm .AMOVWD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
87- arm .AMOVWF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
88- arm .AMOVDF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
89- arm .AMOVDW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
90- arm .AMOVFD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
91- arm .AMOVFW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
86+ arm .AMOVWD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv },
87+ arm .AMOVWF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv },
88+ arm .AMOVDF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Conv },
89+ arm .AMOVDW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv },
90+ arm .AMOVFD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Conv },
91+ arm .AMOVFW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Conv },
9292
9393 // Moves.
94- arm .AMOVB : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
95- arm .AMOVD : {gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
96- arm .AMOVF : {gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
97- arm .AMOVH : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
98- arm .AMOVW : {gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Move , 0 , 0 , 0 },
94+ arm .AMOVB : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Move },
95+ arm .AMOVD : {Flags : gc .SizeD | gc .LeftRead | gc .RightWrite | gc .Move },
96+ arm .AMOVF : {Flags : gc .SizeF | gc .LeftRead | gc .RightWrite | gc .Move },
97+ arm .AMOVH : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Move },
98+ arm .AMOVW : {Flags : gc .SizeL | gc .LeftRead | gc .RightWrite | gc .Move },
9999
100100 // In addtion, duffzero reads R0,R1 and writes R1. This fact is
101101 // encoded in peep.c
102- obj .ADUFFZERO : {gc .Call , 0 , 0 , 0 },
102+ obj .ADUFFZERO : {Flags : gc .Call },
103103
104104 // In addtion, duffcopy reads R1,R2 and writes R0,R1,R2. This fact is
105105 // encoded in peep.c
106- obj .ADUFFCOPY : {gc .Call , 0 , 0 , 0 },
106+ obj .ADUFFCOPY : {Flags : gc .Call },
107107
108108 // These should be split into the two different conversions instead
109109 // of overloading the one.
110- arm .AMOVBS : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
111- arm .AMOVBU : {gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
112- arm .AMOVHS : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
113- arm .AMOVHU : {gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv , 0 , 0 , 0 },
110+ arm .AMOVBS : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv },
111+ arm .AMOVBU : {Flags : gc .SizeB | gc .LeftRead | gc .RightWrite | gc .Conv },
112+ arm .AMOVHS : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv },
113+ arm .AMOVHU : {Flags : gc .SizeW | gc .LeftRead | gc .RightWrite | gc .Conv },
114114
115115 // Jumps.
116- arm .AB : {gc .Jump | gc .Break , 0 , 0 , 0 },
117- arm .ABL : {gc .Call , 0 , 0 , 0 },
118- arm .ABEQ : {gc .Cjmp , 0 , 0 , 0 },
119- arm .ABNE : {gc .Cjmp , 0 , 0 , 0 },
120- arm .ABCS : {gc .Cjmp , 0 , 0 , 0 },
121- arm .ABHS : {gc .Cjmp , 0 , 0 , 0 },
122- arm .ABCC : {gc .Cjmp , 0 , 0 , 0 },
123- arm .ABLO : {gc .Cjmp , 0 , 0 , 0 },
124- arm .ABMI : {gc .Cjmp , 0 , 0 , 0 },
125- arm .ABPL : {gc .Cjmp , 0 , 0 , 0 },
126- arm .ABVS : {gc .Cjmp , 0 , 0 , 0 },
127- arm .ABVC : {gc .Cjmp , 0 , 0 , 0 },
128- arm .ABHI : {gc .Cjmp , 0 , 0 , 0 },
129- arm .ABLS : {gc .Cjmp , 0 , 0 , 0 },
130- arm .ABGE : {gc .Cjmp , 0 , 0 , 0 },
131- arm .ABLT : {gc .Cjmp , 0 , 0 , 0 },
132- arm .ABGT : {gc .Cjmp , 0 , 0 , 0 },
133- arm .ABLE : {gc .Cjmp , 0 , 0 , 0 },
134- obj .ARET : {gc .Break , 0 , 0 , 0 },
116+ arm .AB : {Flags : gc .Jump | gc .Break },
117+ arm .ABL : {Flags : gc .Call },
118+ arm .ABEQ : {Flags : gc .Cjmp },
119+ arm .ABNE : {Flags : gc .Cjmp },
120+ arm .ABCS : {Flags : gc .Cjmp },
121+ arm .ABHS : {Flags : gc .Cjmp },
122+ arm .ABCC : {Flags : gc .Cjmp },
123+ arm .ABLO : {Flags : gc .Cjmp },
124+ arm .ABMI : {Flags : gc .Cjmp },
125+ arm .ABPL : {Flags : gc .Cjmp },
126+ arm .ABVS : {Flags : gc .Cjmp },
127+ arm .ABVC : {Flags : gc .Cjmp },
128+ arm .ABHI : {Flags : gc .Cjmp },
129+ arm .ABLS : {Flags : gc .Cjmp },
130+ arm .ABGE : {Flags : gc .Cjmp },
131+ arm .ABLT : {Flags : gc .Cjmp },
132+ arm .ABGT : {Flags : gc .Cjmp },
133+ arm .ABLE : {Flags : gc .Cjmp },
134+ obj .ARET : {Flags : gc .Break },
135135}
136136
137137func proginfo (p * obj.Prog ) {
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